RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 6 TIMER ARRAY UNIT 6.4.5 Timer interrupt and TOmn pin output at count operation start In the interval timer mode or capture mode, the MDmn0 bit in the TMRmn register sets whether or not to generate a timer interrupt at count start. When MDmn0 is set to 1, the count operation start timing can be known by the timer interrupt (INTTMmn) generation. In the other modes, neither timer interrupt at count operation start nor TOmn output is controlled. Figures 6-46 and 6-47 show operation examples when the interval timer mode (TOEmn = 1, TOMmn = 0) is set. TCRmn TEmn INTTMmn TOmn Figure 6-48. When MDmn0 Is Set to 1 Count operation start When MDmn0 is set to 1, a timer interrupt (INTTMmn) is output at count operation start, and TOmn performs a toggle operation. TCRmn TEmn INTTMmn TOmn Figure 6-49. When MDmn0 Is Set to 0 Count operation start When MDmn0 is set to 0, a timer interrupt (INTTMmn) is not output at count operation start, and TOmn does not change either. After counting one cycle, INTTMmn is output and TOmn performs a toggle operation. Remark m: Unit number (m = 0 to 2) n: Channel number (n = 0 to 7) R01UH0317EJ0004 Rev. 0.04 399 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 6 TIMER ARRAY UNIT 6.5 Channel Input (TImn Pin) Control 6.5.1 TImn edge detection circuit (1) Edge detection basic operation timing Edge detection circuit sampling is done in accordance with the operation clock (fMCK). fCLK Operation clock (fMCK) Synchronized (noise filter) internal TImn signal Rising edge detection internal trigger Falling edge detection internal trigger Remark m: Unit number (m = 0 to 2) n: Channel number (n = 0 to 7) Figure 6-50. Edge Detection Basic Operation Timing R01UH0317EJ0004 Rev. 0.04 400 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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19.2 Configuration of DMA Controlle
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