RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF) (2) LIN-UART1 P11/TI11/ LRxD1/INTPLR1 P132/TI20/ LRxD1/INTPLR1 P84/TI11 P140/TI11 P64/TI11 P60/TI20 P30/TI20 Figure 13-31. Port Configuration of LIN Reception Manipulation Selector Port Mode PM11 Selector Port Mode PM132 Selector Port Mode PM84 PM140 PM64 Selector Port Mode PM60 PM30 Selector SUARTF1 Selector Selector SUARTF1 0: Selects P11 1: Selects P132 00: Selects P11 01: Selects P84 10: Selects P140 11: Selects P64 00: Selects P60 01: Selects P32 10: Selects P132 A summary of the peripheral functions to be used in LIN communication operation is given below. LIN-UART1 reception pin interrupt (INTPLR1); Wakeup signal detection Purpose: Detecting wakeup signal edges and detecting the start of communication Asynchronous serial interface LIN-UART1 LRxD1 input INTPLR1 input TI11 input TI20 input Remarks 1. Figure 13-31 shows the port configuration when in BF reception enable mode during communication (UFnMD1, UFnMD0 = 10B). 2. The above is the port configuration of LIN reception manipulation for R5F10DPJXFB. The port configuration of LIN reception manipulation differs in depending on the product. R01UH0317EJ0004 Rev. 0.04 729 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF) 13.5.5 BF transmission Figure 13-32 describes the processing of BF transmission in LIN communication. Figure 13-32. BF Transmission Processing Flow START Baud rate setting (UFnCTL1 register) Transmit data level, BF length settings (UFnOPT0 register) Various mode settings (UFnOPT1) Noise filter, INTLTn timing settings (UFnOPT2) Various mode settings, enabling transmission (UFnCTL0) Set UFnBTT bit (UFnOPT0) INTLTn signal generated? Caution Set the following values when performing BF transmission. The transmit data level is normal output (UFnTDL = 0). Communication direction control is LSB first (UFnDIR = 1). The parity selection bit is no parity bit output (UFnPS1, UFnPS0 = 00B). The data character length is 8 bits (UFnCL = 1). Transmission interrupt is when starting transmission (UFnITS = 0). END Remarks 1. See (2) of 13.11 Cautions on Use for details of starting LIN-UART. 2. n = 0, 1 Yes R01UH0317EJ0004 Rev. 0.04 730 Feb. 22, 2013 No
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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34.2 64-pin products 1276 R5F10CLDx
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RL78/D1A User’s Manual: Hardware
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