RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 11 A/D CONVERTER (5) Successive approximation register (SAR) The SAR register is a register that sets voltage tap data whose values from the comparison voltage generator match the voltage values of the analog input pins, 1 bit at a time starting from the most significant bit (MSB). If data is set in the SAR register all the way to the least significant bit (LSB) (end of A/D conversion), the contents of the SAR register (conversion results) are held in the A/D conversion result register (ADCR). When all the specified A/D conversion operations have ended, an A/D conversion end interrupt request signal (INTAD) is generated. (6) 10-bit A/D conversion result register (ADCR) The A/D conversion result is loaded from the successive approximation register to this register each time A/D conversion is completed, and the ADCR register holds the A/D conversion result in its higher 10 bits (the lower 6 bits are fixed to 0). (7) 8-bit A/D conversion result register (ADCRH) The A/D conversion result is loaded from the successive approximation register to this register each time A/D conversion is completed, and the ADCRH register stores the higher 8 bits of the A/D conversion result. (8) Controller This circuit controls the conversion time of an input analog signal that is to be converted into a digital signal, as well as starting and stopping of the conversion operation. When A/D conversion has been completed, this controller generates INTAD. (9) AVREFP pin This pin inputs an external reference voltage (AVREFP). If using AVREFP as the + side reference voltage of the A/D converter, set the ADREFP1 and ADREFP0 bits of A/D converter mode register 2 (ADM2) to 01. The analog signals input to ANI1 to ANI8 are converted to digital signals based on the voltage applied between AVREFP and the side reference voltage (AVREFM/VSS). In addition to AVREFP, it is possible to select VDD or the internal reference voltage (1.45 V) as the + side reference voltage of the A/D converter. (10) AVREFM pin This pin inputs an external reference voltage (AVREFM). If using AVREFM as the side reference voltage of the A/D converter, set the ADREFM bit of the ADM2 register to 1. In addition to AVREFM, it is possible to select VSS as the side reference voltage of the A/D converter. R01UH0317EJ0004 Rev. 0.04 507 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 11 A/D CONVERTER 11.3 Registers Used in A/D Converter The A/D converter uses the following registers. Peripheral enable register 1 (PER1) A/D converter mode register 0 (ADM0) A/D converter mode register 1 (ADM1) A/D converter mode register 2 (ADM2) 10-bit A/D conversion result register (ADCR) 8-bit A/D conversion result register (ADCRH) Analog input channel specification register (ADS) Conversion result comparison upper limit setting register (ADUL) Conversion result comparison lower limit setting register (ADLL) A/D test register (ADTES) A/D port configuration register (ADPC) R01UH0317EJ0004 Rev. 0.04 508 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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6.8 Operation of Plural Channels of
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RL78/D1A User’s Manual: Hardware
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