RL78/D1A User's Manual: Hardware - Renesas

Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 5 CLOCK GENERATOR
5.7.8 Conditions before clock oscillation is stopped
The following lists the register flag settings for stopping the clock oscillation (disabling external clock input) and
conditions before the clock oscillation is stopped.
High-speed on-chip
oscillator clock
X1 clock
Table 5-10. Conditions Before the Clock Oscillation Is Stopped and Flag Settings
Clock Conditions Before Clock Oscillation Is Stopped
(External Clock Input Disabled)
External main system clock
MCS = 1 or CLS = 1
(The CPU is operating on a clock other than the high-speed on-chip
oscillator clock.)
MCS = 0 or CLS = 1
(The CPU is operating on a clock other than the high-speed system clock.)
XT1 clock CLS = 0
(The CPU is operating on a clock other than the subsystem clock.)
Flag Settings of SFR
Register
HIOSTOP = 1
MSTOP = 1
XTSTOP = 1
R01UH0317EJ0004 Rev. 0.04 312
Feb. 22, 2013