RL78/D1A User's Manual: Hardware - Renesas

Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 4 PORT FUNCTIONS
TIS271 TIS270
Figure 4-66. Format of TOS20 and TOS21 Registers (2/2)
TI27 (TAU unit2 CH7) alternate pin selection
0 0 P93
0 1 P37
1 0 P62
Other than above Setting prohibited (same as “00” setting)
Considering direct LED driving, or other large current application, 16-bit resolution PWM outputs are also alternated to
the SM pins. When configure pin function, the policy is that odd TO (ch1,3,5,7) of TAU should be output with higher priority.
In addition, 4 kinds of output with different periods using different master CH’s can be achieved if by this means.
(3) Timer input select else register (TISELSE)
This register provides below selection function.
(a) TAU unit 0 channel5 input selection
The input source can be timer input signal (TI05) from port or internal/external clock.
(b) Timer conjunction function of timer output to timer input just like 78K0/Dx2.
TAU unit0 CH1 output can be connected to TAU unit0 CH0. This function is controlled by bit6.
TAU unit2 CH1 output can be connected to TAU unit2 CH0. This function is controlled by bit7.
This function is used for measuring speed or taco pulse. If only use timer caupture function to measure, there will
be too many interrupts and increase the loading of software when input is higher (about 8kHz, 125us interrupt
interval). So division of interrupt is necessary. At this usage, one timer is used as capture mode, its output is
internally connected to another timer (operated as external event mode) to generate divided interrupt.
(Refer to TMP2 and TMP3 conjunction function of 78K0/Dx2)
Figure 4-67. Format of TISELSE Registers
Address: FFF3E After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
TISELSE TOTICON1 TOTICON0 0 0 0 0 TI05SEL1 TI05SEL0
TI05SEL1 TI05SEL0 TIS051 TIS050 TAU unit0 CH5 input alternate selection
0 0 0 0 P05
0 0 0 1 P82
0 0 1 0 P96
0 1 x x Low-speed on-chip clock (fIL)
1 0 x x Sub system clock (fSUB)
1 1 x x Main external clock (fEX)
Other than above Setting prohibited (same as “0000” setting)
Considering the below purposes, every peripheral clock is connected to TI05 of TAU0
Low-speed on-chip clock: For Frequency Detection of Safefy Function.
Sub system clock: For the ultra accuracy trimming of high-speed on-chip oscillator Note
External main clock: For the ultra accuracy trimming of high-speed on-chip oscillator without sub system clock
Note
Note: Count present operation frequency by timer. It is possible to change trimming code by access HIOTRM register.
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Feb. 22, 2013