RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 25 SAFETY FUNCTIONS Note Code flash memory, RAM and Reserved address of each product are as follows. Products Code flash memory RAM Reserved (00000H to xxxxxH) (yyyyyH to FFEFFH) Specific area Other area Read access: No error is Read access: Invalid detected. But value 0FFH is read always access is detected. Fetching instruction: Fetching instruction: Invalid access is Illegal instruction execution is detected and detected. internal reset generated Write access: Invalid (RESF.TRAP bit flag set to 1) access is detected. R5F10CGBxFB 24576 × 8 bits (00000H to 05FFFH) R5F10CGCxFB, 32768 × 8 bits R5F10DGCxFB (00000H to 07FFFH) R5F10CGDxFB, 49152 × 8 bits R5F10DGDxFB, (00000H to 0BFFFH) R5F10CLDxFB, R5F10DLDxFB, R5F10CMDxFB, R5F10DMDxFB R5F10DGExFB, 65536 × 8 bits R5F10DLExFB, (00000H to 0FFFFH) R5F10CMExFB, R5F10DMExFB, R5F10DPExFB R5F10DMFxFB, 98304 × 8 bits R5F10DPFxFB (00000H to 17FFFH) R5F10DMGxFB, 131072 × 8 bits R5F10DPGxFB (00000H to 1FFFFH) R5F10DMJxFB, 262144 × 8 bits R5F10TPJxFB, (00000H to 3FFFFH) R5F10DPJxFB 2048 × 8 bits (FF700H to FFEFFH) 2048 × 8 bits (FF700H to FFEFFH) 3072 × 8 bits (FF300H to FFEFFH) 4096 × 8 bits (FEF00H to FFEFFH) 6144 × 8 bits (FE700H to FFEFFH) 8192 × 8 bits (FDF00H to FFEFFH) 16384 × 8 bits (FBF00H to FFEFFH) Write access: Invalid access is detected. 40960 x 8 bits (06000H to 0FFFFH) 32768 × 8 bits (08000H to 0FFFFH) 16384 × 8 bits (0C000H to 0FFFFH) All other “Reserved” area than “Specific area” All other “Reserved” area than “Specific area” All other “Reserved” area than “Specific area” Not applicable All “Reserved” area 32768 × 8 bits All other “Reserved” area (18000H to 1FFFFH) than “Specific area” Not applicable All “Reserved” area Not applicable All “Reserved” area R01UH0317EJ0004 Rev. 0.04 1145 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 25 SAFETY FUNCTIONS ● Invalid memory access detection control register (IAWCTL) This register is used to control the detection of invalid memory access and RAM/SFR guard function. IAWEN bit is used in invalid memory access detection function. The IAWCTL register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 25-12. Format of Invalid Memory Access Detection Control Register (IAWCTL) Address: F0078H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 IAWCTL IAWEN 0 GRAM1 GRAM0 0 GPORT GINT GCSC IAWEN Note Control of invalid memory access detection 0 Disable the detection of invalid memory access. 1 Enable the detection of invalid memory access. Note Only writing 1 to the IAWEN bit is enabled, not writing 0 to it after setting it to 1. Remark By specifying WDTON = 1 for the option byte (watchdog timer operation enable), the invalid memory access function is enabled even IAWEN = 0. R01UH0317EJ0004 Rev. 0.04 1146 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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