RL78/D1A User's Manual: Hardware - Renesas

Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 5 CLOCK GENERATOR
Table 5-5. CPU Clock Transition and SFR Register Setting Examples (3/6)
(4) CPU clock changing from high-speed on-chip oscillator clock (B) to high-speed system clock (C)
(Setting sequence of SFR registers)
Status Transition
(B) (C)
Setting Flag of SFR Register
(X1 clock: 1 MHz fX 10 MHz)
(B) (C)
(X1 clock: 10 MHz < fX 20 MHz)
(B) (C)
(external main clock)
CMC Register Note 1 OSTS CSC
EXCLK OSCSEL AMPH
Register
Register
MSTOP
OSTC Register
CKC
Register
R01UH0317EJ0004 Rev. 0.04 305
Feb. 22, 2013
MCM0
0 1 0 Note 2 0 Must be checked 1
0 1 1 Note 2 0 Must be checked 1
1 1 Note 2 0 Must not be checked 1
Unnecessary if these registers
are already set
Unnecessary if the CPU is operating with
the high-speed system clock
Notes 1. The clock operation mode control register (CMC) can be changed only once after reset release. This
setting is not necessary if it has already been set.
2. Set the oscillation stabilization time as follows.
Desired the oscillation stabilization time counter status register (OSTC) oscillation stabilization time
Oscillation stabilization time set by the oscillation stabilization time select register (OSTS)
Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see
CHAPTER 32 ELECTRICAL SPECIFICATIONS (J GRADE PRODUCT) (TARGET) and CHAPTER 33
ELECTRICAL SPECIFICATIONS (L GRADE PRODUCT) (TARGET).
(5) CPU clock changing from high-speed on-chip oscillator clock (B) to subsystem clock (D)
Status Transition
(B) (D)
(XT1 clock)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
CMC
Register Note
CSC Register Waiting for CKC Register
Oscillation
OSCSELS XTSTOP
Stabilization
CSS
1 0 Necessary 1
Note The clock operation mode control register (CMC) can be written only once by an 8-bit memory manipulation
instruction after reset release.
Remark (A) to (J) in Table 5-5 correspond to (A) to (J) in Figure 5-20.
Unnecessary if the CPU is operating
with the subsystem clock