RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-11. Format of Serial Status Register mn (SSRmn) (2/2) Address: F0100H, F0101H (SSR00), F0102H, F0103H (SSR01), After reset: 0000H R F0130H, F0131H (SSR10), F0132H, F0133H (SSR11) Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SSRmn 0 0 0 0 0 0 0 0 0 TSF mn OVF mn R01UH0317EJ0004 Rev. 0.04 575 Feb. 22, 2013 BFF mn Overrun error detection flag of channel n 0 0 0 PEF mn 0 No error occurs. 1 An overrun error occurs. Receive data stored in the SDRmn register is not read and transmit data is written or the next receive data is written. Transmit data is not ready for slave transmission or reception in the CSI mode. This is a cumulative flag and is not cleared until 1 is written to the OVCTmn bit of the SIRmn register. PEF mn 0 No error occurs. 1 ACK is not detected (during I 2 C transmission). Parity error detection flag of channel 11 1 is written to the PECTmn bit of the SIRmn register. No ACK signal is returned from the slave channel at the ACK reception timing during I2C transmission (ACK is not detected). Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 1), PEF bit is SSRn only OVF mn
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 12 SERIAL ARRAY UNIT (7) Serial flag clear trigger register mn (SIRmn) SIRmn is a trigger register that is used to clear each error flag of channel n. When each bit (FECTmn, PECTmn, OVCTmn) of this register is set to 1, the corresponding bit (FEFmn, PEFmn, OVFmn) of serial status register mn is cleared to 0. Because SIRmn is a trigger register, it is cleared immediately when the corresponding bit of SSRmn is cleared. SIRmn can be set by a 16-bit memory manipulation instruction. The lower 8 bits of SIRmn can be set with an 8-bit memory manipulation instruction with SIRmnL. Reset signal generation clears this register to 0000H. Figure 12-12. Format of Serial Flag Clear Trigger Register mn (SIRmn) Address: F0104H, F0105H (SIR00), F0106H, F0107H (SIR01), After reset: 0000H R/W F0134H, F0135H (SIR10), F0136H, F0137H (SIR11) Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SIRmn 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PEC Tmn OVC Tmn 0 No trigger operation 1 Clears the OVFmn bit of the SSRmn register to 0. Clear trigger of overrun error flag of channel n PECT11 Clear trigger of parity error of SCL11 0 No trigger operation 1 Clears PEF11 bit of SSR11 register to 0. Cautions 1. Be sure to clear bits 15 to 2 of SIRmn to “0”. 2. Only the error flag set to the SSRn register is cleared by using the SIRmn register. When a clear operation is performed for an error flag that is not set and when a new error is detected between reading the error flag and the clear operation, the error flag may be erased. Remarks 1. When the SIRmn register is read, 0000H is always read. 2. When writing “1” to a clear trigger and setting (1) the corresponding error flag occur simultaneously, setting the error flag takes precedence. 3. m: Unit number (m = 0, 1), n: Channel number (n = 0, 1) R01UH0317EJ0004 Rev. 0.04 576 Feb. 22, 2013 OVC Tmn
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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34.2 64-pin products 1276 R5F10CLDx
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RL78/D1A User’s Manual: Hardware
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