RL78/D1A User's Manual: Hardware - Renesas

Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF)
13.9 Receive Data Noise Filter
The probability of malfunctioning due to noise becomes high with UART reception, because no communication clock
exists. The noise filter is used to eliminate noise in a communication bus and reduce false reception of data. The noise
filter becomes valid by clearing the receive data noise filter use selection bit (UFnRXFL) to “0”.
A start bit and receive data input from a serial data input pin (LRxDn) are sampled with a clock (prescaler clock) divided
by using a prescaler.
When the same sampling value is read twice, the match detector output changes and the receive data is sampled as
the input data. Therefore, data not exceeding 2 clock width is judged to be noise and is not delivered to the internal circuit
(see Figure 13-68). See 13.10 (1) (a) Prescaler clock (fUCLK) regarding the base clock.
LRxDn pin
Prescaler clock
fCLK
RESET
Prescaler clock
(fUCLK)
fCLK
LRxDn pin
FF1
FF2
FF3
FF4
Remark n = 0, 1
D
Figure 13-70. Noise Filter Circuit Example
FF1 FF2 FF3
R
D
CKE
R
D
CKE
R
FF4
LE
D
CKE
R
UFnRXFL bit
Figure 13-71. Noise Filter Timing Chart Example (UFnPRS = 1)
Mismatch
(judged as noise)
Receive data
R01UH0317EJ0004 Rev. 0.04 771
Feb. 22, 2013
1
0
Mismatch
(judged as noise)