RL78/D1A User's Manual: Hardware - Renesas

R01UH0317EJ0004 Rev. 0.04 1306
Feb. 22, 2013
Necessary WAIT I/O register(SFR) name R/W Bit R/W
Address
READ(MIN.) READ(MAX.) WRITE(MIN.) WRITE(MAX.)
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1 8 16 7 6 5 4 3 2 1 0
Retry-number 2 +1
where the retry-number is calculated according
F04EA C1MIDL14 (CAN1 message ID register 14L) - - E - - - - - - - -
to the following method: (Abort under radix point)
For read
F04EC C1MIDH14 (CAN1 message ID register 14H) - - E - - - - - - - -
Min. (1/fCAN) 3/ (1/fCLK)
Max. (1/fCAN) 4/ (1/fCLK)
F04EE C1MCTRL14 (CAN1 message control register 14) - - E - - - - - - - -
For 8 bit-write
F04F0
C1MDB0115 (CAN1 message data byte 01 register 15) - - E - - - - - - - -
Min. (1/fCAN) 4/ (1/fCLK)
Max. (1/fCAN) 5/ (1/fCLK)
C1MDB015 - E - - - - - - - - -
For 16 bit-write
Min. (1/fCAN) 2/ (1/fCLK)
F04F1 C1MDB115 - E - - - - - - - - -
Max. (1/fCAN) 3/ (1/fCLK)
F04F2
C1MDB2315 (CAN1 message data byte 23 register 15) - - E - - - - - - - -
C1MDB215 - E - - - - - - - - -
F04F3 C1MDB315 - E - - - - - - - - -
F04F4
C1MDB4515 (CAN1 message data byte 45 register 15) - - E - - - - - - - -
C1MDB415 - E - - - - - - - - -
F04F5 C1MDB515 - E - - - - - - - - -
F04F6
C1MDB6715 (CAN1 message data byte 67 register 15) - - E - - - - - - - -
C1MDB615 - E - - - - - - - - -
F04F7 C1MDB715 - E - - - - - - - - -
F04F8 C1MDLC15 (CAN1 message data length register 15) - E - - - - - - - - -
F04F9 C1MCONF15 (CAN1 message Configuration register 15) - E - - - - - - - - -
F04FA C1MIDL15 (CAN1 message ID register 15L) - - E - - - - - - - -
F04FC C1MIDH15 (CAN1 message ID register 15H) - - E - - - - - - - -
F04FE C1MCTRL15 (CAN1 message control register 15) - - E - - - - - - - -
F05C0 C0GMCTRL (CAN0 global module control register) - - E - - - - - - - -
F05C6 C0GMABT (CAN0 global block transmission control register) - - E - - - - - - - -
F05C8 C0GMABTD (CAN0 global block transmission delay setting register) - E - - - - - - - - -
F05CE C0GMCS (CAN0 global module clock select register) - E - - - - - - - - -
F05D0 C0MASK1L (CAN0 module mask 1 register L) - - E - - - - - - - -
F05D2 C0MASK1H (CAN0 module mask 1 register H) - - E - - - - - - - -
F05D4 C0MASK2L (CAN0 module mask 2 register L) - - E - - - - - - - -
F05D6 C0MASK2H (CAN0 module mask 2 register H) - - E - - - - - - - -
F05D8 C0MASK3L (CAN0 module mask 3 register L) - - E - - - - - - - -
F05DA C0MASK3H (CAN0 module mask 3 register H) - - E - - - - - - - -
1306
RL78/D1A APPENDIX A NUMBER OF WAIT CYCLES TO ACCESS I/O REGISTERS
Specifications in this document are tentative and subject to change.
Under development Preliminary document