RL78/D1A User's Manual: Hardware - Renesas

Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 32 ELECTRICAL SPECIFICATIONS (J GRADE PRODUCT) (TARGET)
32.7.3 POR characteristics
TA = -40 to +85 °C
Item Symbol Conditions MIN. TYP. MAX. Unit
Detection voltage
VPOR
VPDR
1.48
1.47
1.51
1.5
1.54
1.53
V
V
Detection delay TPD 200 s
Minimum pulse width TPW Necessarywidthofinternalvoltage
drop down below VPDR
200 s
Caution LVD reset or external RESET must be used during power supply rising up to 2.7V.
32.7.4 LVD characteristics
TA = -40 to +85 C, VPDR EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V
Items Conditions Symbols MIN. TYP. MAX
.
Unit
RESET and
VPOC0,1,2 = 0,1,1 Power down Reset Voltage: 2.7 V VLVI5 2.70 2.75 2.81 V
INTMODE
LVIS0,1 = 1,0
(+0.1 V)
Power on Reset Release Voltage
Power down Interrupt Voltage
VLVI4
2.86
2.80
2.92
2.86
2.97
2.91
V
V
LVIS0,1 = 0,1
(+0.2 V)
Power on Reset Release Voltage
Power down Interrupt Voltage
VLVI3
2.96
2.90
3.02
2.96
3.08
3.02
V
V
LVIS0,1 = 0,0
(+1.2 V)
Power on Reset Release Voltage
Power down Interrupt Voltage
VLVI0
3.98
3.90
4.06
3.98
4.14
4.06
V
V
Detection Delay time TLD 200 s
Minimum pulse width Necessarywidthofinternalvoltage drop down below TLW 200 s
VPDR
32.8 Data Retention Characteristics
TA = -40 to +85 C
Items Symbols Conditions MIN. TYP. MAX. Unit
Data retention supply voltage VDDDR 1.5 Note1 5.5 V
Note The value depends on the POC detection voltage. When the voltage drops, the data is retained until a POC
reset is effected, but data is not retained when a POC reset is effected.
VDD
STOP instruction execution
Standby release signal
(interrupt request)
Figure 32-13. STOP Mode Data Retention timming
STOP mode
Data retention mode
VDDDR
Operation mode
R01UH0317EJ0004 Rev. 0.04 1241
Feb. 22, 2013