RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 24 VOLTAGE DETECTOR (2) Voltage detection level register (LVIS) This register selects the voltage detection level. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation input sets this register to 00H/01H/81H Note1 . Figure 24-3. Format of Voltage Detection Level Select Register (LVIS) Address: FFFAAH After reset: 00H/01H/81H Note 1 R/W Symbol 6 5 4 3 2 1 LVIS LVIMD 0 0 0 0 0 0 LVILV LVIMD Note 2 0 Interrupt mode 1 Reset mode Operation mode of voltage detection LVILV Note 2 LVD detection level 0 High-voltage detection level (VLVDH) 1 Low-voltage detection level (VLVDL or VLVD) Notes 1. The reset value changes depending on the reset source and the setting of the option byte. This register is not cleared (00H) by LVD reset. The generation of reset signal other than an LVD reset sets as follows. When option byte LVIMDS1, LVIMDS0 = 1, 0: 00H When option byte LVIMDS1, LVIMDS0 = 1, 1: 81H When option byte LVIMDS1, LVIMDS0 = 0, 1: 01H 2. Writing “0” can only be allowed when LVIMDS1 and LVIMDS0 are set to 1 and 0 (interrupt and reset mode) by the option byte. In other cases, writing is not allowed and the value is switched automatically when reset or interrupt is generated. Cautions 1. Only rewrite the value of the LVIS register after setting the LVISEN bit (bit 7 of the LVIM register) to 1. 2. Specify the LVD operation mode and detection voltage (VLVDH, VLVDL) by using the option byte (000C1H). Table 24-1 shows the option byte (000C1H) settings. For details about the option byte, see CHAPTER 27 OPTION BYTE. R01UH0317EJ0004 Rev. 0.04 1117 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 24 VOLTAGE DETECTOR Table 24-1. LVD Operation Mode and Detection Voltage Settings for User Option Byte (000C1H/020C1H) (1/2) Address: 000C1H/020C1H Note 7 6 5 4 3 2 1 0 VPOC2 VPOC1 VPOC0 CLKMB LVIS1 LVIS0 LVIMDS1 LVIMDS0 LVD setting (interrupt & reset mode) Detection voltage Option byte Setting Value VLVDH VLVDL LVIMDS1 LVIMDS0 VPOC2 VPOC1 VPOC0 LVIS1 LVIS0 Rising Falling Falling edge edge edge 2.92 V 2.86 V 2.75 V 1 0 0 1 1 1 0 3.02 V 2.96 V 0 1 4.06 V 3.98 V 0 0 Other than above Setting prohibited LVD setting (reset mode) Detection voltage Option byte Setting Value VLVD LVIMDS1 LVIMDS0 VPOC2 VPOC1 VPOC0 LVIS1 LVIS0 Rising edge Falling edge 2.81 V 2.75 V 1 1 0 1 1 1 1 2.92 V 2.86 V 0 1 1 1 0 3.02 V 2.96 V 0 1 1 0 1 3.13 V 3.06 V 0 0 1 0 0 3.75 V 3.67 V 0 1 0 0 0 4.06 V 3.98 V 0 1 1 0 0 Other than above Setting prohibited Note Set the same value as 000C1H to 020C1H when the boot swap operation is used because 000C1H is replaced by 020C1H. R01UH0317EJ0004 Rev. 0.04 1118 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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