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RL78/D1A User's Manual: Hardware - Renesas

RL78/D1A User's Manual: Hardware - Renesas

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Under development<br />

Preliminary document<br />

Specifications in this document are tentative and subject to change.<br />

<strong>RL78</strong>/<strong>D1A</strong> CHAPTER 14 CAN CONTROLLER<br />

(3) Synchronizing data bit<br />

- The receiving node establishes synchronization by a level change on the bus because it does not have a sync<br />

signal.<br />

- The transmitting node transmits data in synchronization with the bit timing of the transmitting node.<br />

(a) Hard-synchronization<br />

This synchronization is established when the receiving node detects the start of frame in the interframe space.<br />

- When a falling edge is detected on the bus, that TQ means the sync segment and the next segment is the<br />

prop segment. In this case, synchronization is established regardless of SJW.<br />

Figure 14-20. Hard-synchronization at Recognition of Dominant Level during Bus Idle<br />

CANbus<br />

Bit timing<br />

Interframe space<br />

Sync<br />

segment<br />

Prop<br />

segment<br />

Start of frame<br />

Phase<br />

segment 1<br />

Phase<br />

segment 2<br />

R01UH0317EJ0004 Rev. 0.04 806<br />

Feb. 22, 2013

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