RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 6 TIMER ARRAY UNIT (16) Timer output select register (TOS00, TOS01, TOS10, TOS11, TOS20, TOS21) These registers are used for alternate switch of TAU output pins. TOS00 to TOS01 is for TAU unit0, TOS10 to TOS11 for TAU unit1, TOS20 to TOS21 for TAU unit2. Figure 6-33. Format of Timer Output Select Register 0 (TOS0) (1/2) Address: F0076H After reset: 00H R/W: (Note: Bits 1 and 5 are read only bit.) Symbol 7 6 5 4 3 2 1 0 TOS00 TOS031 TOS030 0 TOS020 TOS011 TOS010 0 TOS000 Address: F0077H After reset: 00H R/W: (Note: Bits 1 and 5 are read only bit.) Symbol 7 6 5 4 3 2 1 0 TOS01 TOS071 TOS070 0 TOS060 TOS051 TOS050 0 TOS040 TOS000 TO00 (TAU unit0 CH0) alternate pin selection 0 P00 1 P136 TOS011 TIS010 TO01 (TAU unit0 CH1) alternate pin selection 0 0 P01 0 1 P80 1 0 P94 Other than above Setting prohibited (same as “00” setting) TOS020 TO02 (TAU unit0 CH2) alternate pin selection 0 P02 1 P50 TOS031 TOS030 TO03 (TAU unit0 CH3) alternate pin selection 0 0 P03 0 1 P81 1 0 P95 1 1 P70 TOS040 TO04 (TAU unit0 CH4) alternate pin selection 0 P04 1 P51 TOS051 TOS050 TO05 (TAU unit0 CH5) alternate pin selection 0 0 P05 0 1 P82 1 0 P96 Other than above Setting prohibited (same as “00” setting) TOS060 TO06 (TAU unit0 CH6) alternate pin selection 0 P06 1 P52 R01UH0317EJ0004 Rev. 0.04 361 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-33. Format of Timer Output Select Register 0 (TOS0) (2/2) TOS071 TOS070 TO07 (TAU unit0 CH7) alternate pin selection 0 0 P07 0 1 P83 1 0 P97 Other than above Setting prohibited (same as “00” setting) R01UH0317EJ0004 Rev. 0.04 362 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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12.5.3 Master transmission/receptio
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19.2 Configuration of DMA Controlle
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