RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 32 ELECTRICAL SPECIFICATIONS (J GRADE PRODUCT) (TARGET) TA = -40 to +85 C, 2.7 V VDD 5.5 V, VSS = 0 V Parameter Symbols Conditions Typ. Max. Unit Supply current, Note 1 IDD2 High speed fCLK = 32 MHz fHOCO = 32 MHz 1.0 8.1 mA halt mode MAIN HALT 2.7 VVDD fHOCO = 4 MHz with PLL Note 3, 4 fX = 4 MHz with PLL fX = 8 MHz with PLL fCLK = 24 MHz fHOCO = 24 MHz fHOCO = 4 MHz with PLL fX = 4 MHz with PLL fX = 8 MHz with PLL 0.8 6.9 mA fCLK = 20 MHz fX = 20 MHz 0.7 6.0 mA fCLK = 8 MHz fHOCO = 8 MHz fX = 8 MHz 0.4 6.3 mA fCLK = 4 MHz fHOCO = 4 MHz fX = 4 MHz 0.35 3.6 mA SUB HALT fCLK = fXT RTC is stopped 1.0 130 A Note 3, 4, 5 = 32.768 kHz RTC is operated by fXT = 32.768KHz 4.0 Supply current, IDD3 RTC and fXT are stopped 0.4 stop mode Note 2 Note 3, STOP 60 A 4 RTC is operated by fXT = 32.768KHz 3.0 Notes 1. The common condition for IDD2: - IDD includes the total current flowing into whole power pins, including the input leakage current flowing when the level of the input pin is fixed to VDD or VSS. - The HALT instruction is executed by the program in the code flash. - The specification shows the stable current during HALT mode. 2. The common condition for IDD3: - IDD includes the total current flowing into whole power pins, including the input leakage current flowing when the level of the input pin is fixed to VDD or VSS. - The STOP instruction is executed by the program in the code flash during MAIN RUN operation. - The spec shows the stable current during STOP mode. 3. The typical value is that when Ta=+25deg.C and VDD=5.0 V. Peripheral devices and the data flash are stopped. 4. The maximum value is that when all peripheral devices are operating. But the A/D converter, LCD circuit, stepper motor circuit, the data flash and the code flash are stopped. The 16-bit wakeup timer operates with fLOCO. 5. fX and fHOCO are stopped. R01UH0317EJ0004 Rev. 0.04 1215 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 32 ELECTRICAL SPECIFICATIONS (J GRADE PRODUCT) (TARGET) TA = -40 to +85 C, 2.7 V VDD 5.5 V, VSS = 0 V Parameter Symbols Conditions Typ. Max. Unit WDT operating IWDT 0.25 1.0 A Note 1 current ADC operating Note 2 current LCD operating Note 3 Current ZPD operating Note 4 current IADC ILCD fLCD = fSUB, IZPD Normal mode VDD = 5.0 V 1.3 1.7 mA Low voltage mode VDD = 3.0 V 0.5 0.7 mA VDD = 5.0 V 100 140 A LCD clock = 512 Hz VDD = 3.0 V 90 130 A One ZPD operated VDD = 5.0 V 150 600 A VDD = 3.0 V 100 500 A Four ZPDs operated VDD = 5.0 V 500 2000 A VDD = 3.0 V 400 1600 A Notes 1. Current flowing only to the watchdog timer. The maximum specification of IDD1, IDD2 and IDD3 include IWDT. 2. Current flowing only to the A/D converter.The current value of the RL78/D1A is the sum of IDD and IADC when the A/D converter operates. 3. Current flowing only to the LCD controller/driver circuit. The current value of the RL78/D1A is the sum of IDD and ILCD when the LCD controller/driver circuit operates. 4. Current flowing only to the ZPD circuit. The current value of the RL78/D1A is the sum of IDD and IZPD when the ZPD circuit operates. R01UH0317EJ0004 Rev. 0.04 1216 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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