RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 17 SOUND GENERATOR 17.4 Sound Generator Application Hints This section provides supplementary programming information. 17.4.1 Initialization To enable the Sound Generator, set SG0CTL.PWR to 1. This connects the SG0 to the clock SG0CLK. Check bit SG0CTL.OS. When SG0CTL.OS is 0, the signal at pin SGO is a symmetrical square waveform with the frequency ftone. When SG0CTL.OS is 1, the signal at pin SGO is composed of the tone signal and PWM pulses. The frequency data registers SG0FL and SG0FH provide the buffer values for the counters. The combined value represents the frequency of the tone. 17.4.2 Start and stop sound The sound is started by writing a non-zero value to the volume register SG0PWM. Before starting the sound, all other register settings must be made. The sound is stopped by writing 0000H to the volume register SG0PWM. The sound is stopped regardless of the current value of amplitude output or frequency output. Thus, the sound can be stopped quickly, even if a very low sound frequency is chosen. 17.4.3 Change sound volume The sound volume is changed by writing a new value to register SG0PWM. The new volume takes effect with the next edge of the tone pulse (rising or falling). 17.4.4 Generate special sounds To generate special sounds (like blinker clicks etc.), frequency and volume can be changed simultaneously. To change the frequency of a sound that has already started: 1. Write to the frequency registers SG0FL and SG0FH separately in 16-bit mode. 2. Write to the volume register SG0PWM. R01UH0317EJ0004 Rev. 0.04 1009 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 18 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR CHAPTER 18 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 18.1 Functions of Multiplier and Divider/Multiply-Accumulator The multiplier and divider/multiply-accumulator has the following functions. • 16 bits 16 bits = 32 bits (Unsigned) • 16 bits 16 bits = 32 bits (Signed) • 16 bits 16 bits + 32 bits = 32 bits (Unsigned) • 16 bits 16 bits + 32 bits = 32 bits (Signed) • 32 bits 32 bits = 32 bits, 32-bits remainder (Unsigned) 18.2 Configuration of Multiplier and Divider/Multiply-Accumulator The multiplier and divider/multiply-accumulator consists of the following hardware. Registers Table 18-1. Configuration of Multiplier and Divider/Multiply-Accumulator Item Configuration Multiplication/division data register A (L) (MDAL) Multiplication/division data register A (H) (MDAH) Multiplication/division data register B (L) (MDBL) Multiplication/division data register B (H) (MDBH) Multiplication/division data register C (L) (MDCL) Multiplication/division data register C (H) (MDCH) Control register Multiplication/division control register (MDUC) Figure 18-1 shows a block diagram of the multiplier and divider/multiply-accumulator. R01UH0317EJ0004 Rev. 0.04 1010 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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34.2 64-pin products 1276 R5F10CLDx
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RL78/D1A User’s Manual: Hardware
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RL78/D1A User's Manual: Hardware - Renesas

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