RL78/D1A User's Manual: Hardware - Renesas

Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 14 CAN CONTROLLER
Table 14-18. Bit Configuration of CAN Module Registers (2/4)
Address Symbol Bit 7/15 Bit 6/14 Bit 5/13 Bit 4/12 Bit 3/11 Bit 2/10 Bit 1/9 Bit 0/8
000F05E8H C0INTS(R) 0 0 CINTS5 CINTS4 CINTS3 CINTS2 CINTS1 CINTS0
000F05E9H 0 0 0 0 0 0 0 0
000F05EAH C0BRP TQPRS [7:0]
000F05ECH C0BTR 0 0 0 0 TSEG1 [3:0]
000F05EDH 0 0 SJW [1:0] 0 TSEG2 [2:0]
000F05EEH C0LIPT LIPT [7:0]
000F05F0H C0RGPT(W) 0 0 0 0 0 0 0 Clear
ROVF
000F05F1H 0 0 0 0 0 0 0 0
000F05F0H C0RGPT(R) 0 0 0 0 0 0 RHPM ROVF
000F05F1H RGPT [7:0]
000F05F2H C0LOPT LOPT [7:0]
000F05F4H C0TGPT(W) 0 0 0 0 0 0 0 Clear
TOVF
000F05F5H 0 0 0 0 0 0 0 0
000F05F4H C0TGPT(R) 0 0 0 0 0 0 THPM TOVF
000F05F5H TGPT [7:0]
000F05F6H C0TS(W) 0 0 0 0 0 Clear Clear Clear
TSLOCK TSSEL TSEN
000F05F7H 0 0 0 0 0 Set Set Set
TSLOCK TSSEL TSEN
000F05F6H C0TS(R) 0 0 0 0 0 TSLOCK TSSEL TSEN
000F05F7H 0 0 0 0 0 0 0 0
Caution The actual register address is calculated as follows:
Register Address = Global Register Area Offset (CH dependent) + Offset Address as listed in table
above
Remark (R) When read
(W) When write
R01UH0317EJ0004 Rev. 0.04 836
Feb. 22, 2013