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RL78/D1A User's Manual: Hardware - Renesas

RL78/D1A User's Manual: Hardware - Renesas

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Under development<br />

Preliminary document<br />

Specifications in this document are tentative and subject to change.<br />

<strong>RL78</strong>/<strong>D1A</strong> CHAPTER 22 RESET FUNCTION<br />

22.2 CLM Reset Control Flag Register<br />

The CLM Reset Control Flag Register (RESFCLM) checks whether an internal reset generates. The CLKRF bit is<br />

cleared when the RESFCLM is cleared. The register can be accessed in 8-bit unit. The CLKRF bit is cleared by RESET<br />

input, power-on-reset (POR) circuit, and reading the register.<br />

Figure 22-6. Format of CLM Reset Control Flag Register (RESFCLM)<br />

Address: F00FAH After reset: 00H Note 1 R<br />

Symbol 7 6 5 4 3 2 1 0<br />

RESFCLM 0 0 0 0 0 0 0 CLKRF<br />

CLKRF Internal reset request by clock monitor<br />

0 Internal reset request is not generated, or the RESFCLM is cleared.<br />

1 Internal reset request is generated.<br />

Note 1. The value after reset varies depending on the reset source.<br />

R01UH0317EJ0004 Rev. 0.04 1106<br />

Feb. 22, 2013

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