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RL78/D1A User's Manual: Hardware - Renesas

RL78/D1A User's Manual: Hardware - Renesas

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Under development<br />

Preliminary document<br />

Specifications in this document are tentative and subject to change.<br />

<strong>RL78</strong>/<strong>D1A</strong> CHAPTER 12 SERIAL ARRAY UNIT<br />

(Essential)<br />

(Essential)<br />

(Selective)<br />

(Selective)<br />

(Selective)<br />

(Selective)<br />

(Selective)<br />

(Selective)<br />

(Selective)<br />

(Essential)<br />

(Essential)<br />

(Essential)<br />

(Essential)<br />

Figure 12-66. Procedure for Resuming Slave Transmission/Reception<br />

Starting setting for resumption<br />

Manipulating target for communication<br />

Port manipulation<br />

Changing setting of SPSm register<br />

Changing setting of SMRmn register<br />

Changing setting of SCRmn register<br />

Clearing error flag<br />

Changing setting of SOEm register<br />

Changing setting of SOm register<br />

Changing setting of SOEm register<br />

Port manipulation<br />

Writing to SSm register<br />

Starting communication<br />

Starting target for communication<br />

Stop the target for communication or wait<br />

until the target completes its operation.<br />

Disable data output of the target channel<br />

by setting a port register and a port<br />

mode register.<br />

Change the setting if an incorrect division<br />

ratio of the operation clock is set.<br />

Change the setting if the setting of the<br />

SMRmn register is incorrect.<br />

Change the setting if the setting of the<br />

SCRmn register is incorrect.<br />

Cleared by using SIRmn register if FEF,<br />

PEF, or OVF flag remains set.<br />

Set the SOEm register and stop the<br />

output of the target channel.<br />

Manipulate the SOmn bit and set an<br />

initial output level.<br />

Set the SOEm register and enable the<br />

output of the target channel.<br />

Enable data output of the target channel<br />

by setting a port register and a port mode<br />

register.<br />

Set the SSmn bit of the target channel to<br />

1 to set SEmn = 1.<br />

Set transmit data to the SDRmn register<br />

and wait for a clock from the master.<br />

Start the target for communication.<br />

Caution Be sure to set transmit data to the SDRpL register before the clock from the master is started.<br />

R01UH0317EJ0004 Rev. 0.04 641<br />

Feb. 22, 2013

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