RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF) Target Baud Rate (bps) Table 13-9. Baud Rate Generator Setting Data (Normal Operation, fCLK = 4 MHz, UFnPRS2 to UFnPRS0 = 0 to 3) (1/2) UFnPRS2 to UFnPRS0 0 1 2 3 UFnBRS11 to ERR UFnBRS11 to ERR UFnBRS11 to ERR UFnBRS11 to UFnBRS00 (%) UFnBRS00 (%) UFnBRS00 (%) UFnBRS00 300 3333 0.01 1667 -0.02 833 0.04 600 3333 0.01 1667 -0.02 833 0.04 417 -0.08 1200 1667 -0.02 833 0.04 417 -0.08 208 0.16 2400 833 0.04 417 -0.08 208 0.16 104 0.16 4800 417 -0.08 208 0.16 104 0.16 52 0.16 9600 208 0.16 104 0.16 52 0.16 26 0.16 19200 104 0.16 52 0.16 26 0.16 13 0.16 31250 64 0.00 32 0.00 16 0.00 8 0.00 38400 52 0.16 26 0.16 13 0.16 7 -6.99 76800 26 0.16 13 0.16 7 -6.99 128000 16 -2.34 8 -2.34 4 -2.34 153600 13 0.16 7 -6.99 312500 6 6.67 1000000 Target Baud Rate (bps) Table 13-9. Baud Rate Generator Setting Data (Normal Operation, fCLK = 4 MHz, UFnPRS2 to UFnPRS0 = 4 to 7) (2/2) UFnPRS2 to UFnPRS0 4 5 6 7 UFnBRS11 to ERR UFnBRS11 to ERR UFnBRS11 to ERR UFnBRS11 to UFnBRS00 (%) UFnBRS00 (%) UFnBRS00 (%) UFnBRS00 300 417 -0.08 208 0.16 104 0.16 52 0.16 600 208 0.16 104 0.16 52 0.16 26 0.16 1200 104 0.16 52 0.16 26 0.16 13 0.16 2400 52 0.16 26 0.16 13 0.16 7 -6.99 4800 26 0.16 13 0.16 7 -6.99 9600 13 0.16 7 -6.99 19200 7 -6.99 31250 4 0.00 38400 76800 128000 153600 312500 1000000 R01UH0317EJ0004 Rev. 0.04 779 Feb. 22, 2013 ERR (%) ERR (%)
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF) (6) Allowable baud rate range during reception The baud rate error range at the destination that is allowable during reception is shown below. Caution The baud rate error during reception must be set within the allowable error range using the following equation. LIN-UARTn transfer rate Minimum allowable transfer rate Maximum allowable transfer rate Figure 13-74 Allowable Baud Rate Range During Reception Latch timing Start bit Bit 0 Bit 1 Bit 7 Parity bit FL 1 data frame (11 × FL) Start bit Bit 0 Bit 1 Bit 7 Parity bit R01UH0317EJ0004 Rev. 0.04 780 Feb. 22, 2013 FLmin FLmax Stop bit Stop bit Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit As shown in Figure 13-74, the receive data latch timing is determined by the counter set using the UFnCTL1 register following start bit detection. The transmit data can be normally received if up to the last data (stop bit) can be received in time for this latch timing. When this is applied to 11-bit reception while the data bit length is 8 bits, the following is the theoretical result. FL = (Brate) 1 Brate: LIN-UARTn baud rate k: Setting value of UFnCTL1 FL: 1-bit data length Latch timing margin: 2 clocks k 2 21k + 2 Minimum allowable transfer rate: FLmin = 11 FL FL = FL 2k 2k
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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RL78/D1A User’s Manual: Hardware
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