RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF) Figure 13-44. Status Interrupt Occurrence Timing upon Successful BF Reception (When UFnBRF = 0) LRxDn input Data sampling UFnFE flag/ UFnOVE flag UFnBSF flag INTLSn LTxDn output LRxDn input Data sampling UFnBRF flag UFnTSF flag Error judgment (internal signal) UFnDCE flag INTLSn Remark n = 0, 1 “0“ Start bit D0 D5 D6 D7 When low-level period is at least 11 bits Figure 13-45. Example of Data Consistency Error Occurrence Timing When UFnBRF = 0 “0“ Start bit Start bit D0 D5 D6 D7 D0 D5 D6 D7 During reception operation R01UH0317EJ0004 Rev. 0.04 743 Feb. 22, 2013 Stop bit Stop bit Stop bit Mismatch detection Next transmission is not performed.
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF) Figure 13-46. Example of Consistency Error Occurrence Timing During BF Transmission When UFnBRF = 1 (If Reception Operation Is Stopped When Input Data “1” Is Detected After Stop Bit (Previous Bit Is “1”)) LTxDn output LRxDn input Data sampling UFnBRF flag “1“ Mismatch Reception operation detection is stopped. UFnTSF flag Error judgment (internal signal) UFnDCE flag INTLSn BF length BF length Next transmission is not performed. Figure 13-47. Example of Consistency Error Occurrence Timing During BF Transmission When UFnBRF = 1 (If During Reception Operation When Input Data “1” Is Detected After Stop Bit (Previous Bit Is “0”)) LTxDn output LRxDn input Data sampling UFnBRF flag UFnTSF flag Error judgment (internal signal) UFnDCE flag INTLSn flag Remark n = 0, 1 “1“ BF length BF length R01UH0317EJ0004 Rev. 0.04 744 Feb. 22, 2013 Stop bit Stop bit Mismatch detection Stop bit Stop bit During reception operation Next transmission is not performed.
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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12.5.3 Master transmission/receptio
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14.9.1 Message reception ..........
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19.2 Configuration of DMA Controlle
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RL78/D1A User’s Manual: Hardware
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