RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 31 INSTRUCTION SET Instruction Mnemonic Group Operands Bytes Increment/ decrement Shift INC DEC INCW DECW Table 31-5. Operation List (12/17) Clocks Operation Flag Note 1 Note 2 Z AC CY r 1 1 r r + 1 !addr16 3 2 (addr16) (addr16) + 1 ES:!addr16 4 3 (ES, addr16) (ES, addr16) + 1 saddr 2 2 (saddr) (saddr) + 1 [HL+byte] 3 2 (HL+byte) (HL+byte) + 1 ES: [HL+byte] 4 3 ((ES:HL) + byte) ((ES:HL) + byte) + 1 r 1 1 r r 1 !addr16 3 2 (addr16) (addr16) 1 ES:!addr16 4 3 (ES, addr16) (ES, addr16) 1 saddr 2 2 (saddr) (saddr) 1 [HL+byte] 3 2 (HL+byte) (HL+byte) 1 ES: [HL+byte] 4 3 ((ES:HL) + byte) ((ES:HL) + byte) 1 rp 1 1 rp rp + 1 !addr16 3 2 (addr16) (addr16) + 1 ES:!addr16 4 3 (ES, addr16) (ES, addr16) + 1 saddrp 2 2 (saddrp) (saddrp) + 1 [HL+byte] 3 2 (HL+byte) (HL+byte) + 1 ES: [HL+byte] 4 3 ((ES:HL) + byte) ((ES:HL) + byte) + 1 rp 1 1 rp rp 1 !addr16 3 2 (addr16) (addr16) 1 ES:!addr16 4 3 (ES, addr16) (ES, addr16) 1 saddrp 2 2 (saddrp) (saddrp) 1 [HL+byte] 3 2 (HL+byte) (HL+byte) 1 ES: [HL+byte] 4 3 ((ES:HL) + byte) ((ES:HL) + byte) 1 SHR A, cnt 2 1 (CY A0, Am1 Am, A7 0) cnt SHRW AX, cnt 2 1 (CY AX0, AXm1 AXm, AX15 0) cnt SHL SHLW A, cnt 2 1 (CY A7, Am Am1, A0 0) cnt B, cnt 2 1 (CY B7, Bm Bm1, B0 0) cnt C, cnt 2 1 (CY C7, Cm Cm1, C0 0) cnt AX, cnt 2 1 (CY AX15, AXm AXm1, AX0 0) cnt BC, cnt 2 1 (CY BC15, BCm BCm1, BC0 0) cnt SAR A, cnt 2 1 (CY A0, Am1 Am, A7 A7) cnt SARW AX, cnt 2 1 (CY AX0, AXm1 AXm, AX15 AX15) cnt Notes 1. When the internal RAM area, SFR area, or extended SFR area is accessed, or for an instruction with no data access. 2. When the program memory area is accessed. Remarks 1. This number of clocks is for when the program is in the internal ROM (flash memory) area. When fetching an instruction from the internal RAM area, the number of clocks is twice the number of clocks plus 3, maximum. 2. cnt indicates the bit shift count. R01UH0317EJ0004 Rev. 0.04 1205 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 31 INSTRUCTION SET Instruction Mnemonic Group Operands Bytes Rotate Bit manipulate Table 31-5. Operation List (13/17) Clocks Operation Flag Note 1 Note 2 Z AC CY ROR A, 1 2 1 (CY, A7 A0, Am1 Am) 1 ROL A, 1 2 1 (CY, A0 A7, Am + 1 Am) 1 RORC A, 1 2 1 (CY A0, A7 CY, Am1 Am) 1 ROLC A, 1 2 1 (CY A7, A0 CY, Am + 1 Am) 1 ROLWC MOV1 AND1 OR1 AX,1 2 1 (CY AX15, AX0 CY, AXm + 1 AXm) 1 BC,1 2 1 (CY BC15, BC0 CY, BCm + 1 BCm) 1 CY, A.bit 2 1 CY A.bit A.bit, CY 2 1 A.bit CY CY, PSW.bit 3 1 CY PSW.bit PSW.bit, CY 3 4 PSW.bit CY CY, saddr.bit 3 1 CY (saddr).bit saddr.bit, CY 3 2 (saddr).bit CY CY, sfr.bit 3 1 CY sfr.bit sfr.bit, CY 3 2 sfr.bit CY CY,[HL].bit 2 1 4 CY (HL).bit [HL].bit, CY 2 2 (HL).bit CY CY, ES:[HL].bit 3 2 5 CY (ES, HL).bit ES:[HL].bit, CY 3 3 (ES, HL).bit CY CY, A.bit 2 1 CY CY A.bit CY, PSW.bit 3 1 CY CY PSW.bit CY, saddr.bit 3 1 CY CY (saddr).bit CY, sfr.bit 3 1 CY CY sfr.bit CY,[HL].bit 2 1 4 CY CY (HL).bit CY, ES:[HL].bit 3 2 5 CY CY (ES, HL).bit CY, A.bit 2 1 CY CY A.bit CY, PSW.bit 3 1 CY CY PSW.bit CY, saddr.bit 3 1 CY CY (saddr).bit CY, sfr.bit 3 1 CY CY sfr.bit CY, [HL].bit 2 1 4 CY CY (HL).bit CY, ES:[HL].bit 3 2 5 CY CY (ES, HL).bit Notes 1. When the internal RAM area, SFR area, or extended SFR area is accessed, or for an instruction with no data access. 2. When the program memory area is accessed. Remark This number of clocks is for when the program is in the internal ROM (flash memory) area. When fetching an instruction from the internal RAM area, the number of clocks is twice the number of clocks plus 3, maximum. R01UH0317EJ0004 Rev. 0.04 1206 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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