RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 14 CAN CONTROLLER Releasing CAN sleep mode by user START CAN stop mode Clear PSMODE1 bit CAN sleep mode Clear PSMODE0 bit END Figure 14-81. Clear CAN Sleep/Stop Mode (In case CAN clock is disabled) Releasing CAN sleep mode by CAN bus active After dominant edge detection PSMODE0 = 0 CINTS5 = 1 Clear CINTS5 bit (In case CAN clock is active) Releasing CAN sleep mode by CAN bus active After dominant edge detection PSMODE0 = 0/1 CINTS5 = 1 Clear PSMODE0 bit Clear CINTS5 bit Remark “In case CAN clock is disabled”: By means of the CPU standby mode, the CAN module clock has been switched off, and the CAN module is in sleep mode. R01UH0317EJ0004 Rev. 0.04 937 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 14 CAN CONTROLLER Figure 14-82. Bus-Off Recovery (Expect Normal Operation Mode with ABT) No START BOFF = 1? Yes Clear all TRQ bits Note Set C0CTRL register (Clear OPMODE) Access to registers other than C0CTRL and C0GMCTRL registers Forced recovery from bus off? Set CCERC bit Set C0CTRL register (Set OPMODE) Wait for recovery from bus off END Yes No Set C0CTRL register (Set OPMODE) Note Clear all TRQ bits when re-initialization of message buffer is executed by clearing RDY bit before bus-off recovery sequence is started. Caution When the transmission from the initialization mode to any operation modes is requested to execute bus-off recovery sequence again in the bus-off recovery sequence, reception error counter is cleared. Therefore it is necessary to detect 11 consecutive recessive-level bits 128 times on the bus again. Remark OPMODE: Normal operation mode, normal operation mode with ABT, receive-only mode, single-shot mode, self-test mode R01UH0317EJ0004 Rev. 0.04 938 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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RL78/D1A User’s Manual: Hardware
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