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RL78/D1A User's Manual: Hardware - Renesas

RL78/D1A User's Manual: Hardware - Renesas

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Under development<br />

Preliminary document<br />

Specifications in this document are tentative and subject to change.<br />

<strong>RL78</strong>/<strong>D1A</strong> CHAPTER 6 TIMER ARRAY UNIT<br />

fCLK<br />

4 4<br />

Timer clock select register 1 (TPS1)<br />

PRS133 PRS132 PRS131 PRS130 PRS123 PRS122 PRS121 PRS120<br />

Peripheral enable<br />

register 0<br />

(PER0)<br />

TI10<br />

TI11<br />

(timer<br />

input<br />

pin Note )<br />

TI12<br />

TI13<br />

TI14<br />

TI15<br />

TI16<br />

TI17<br />

TAU1EN<br />

Noise elimination<br />

enabled/disabled<br />

CK10<br />

CK11<br />

CK12<br />

CK13<br />

Channel 0<br />

TNFEN11<br />

Operation clock<br />

selection<br />

Channel 1<br />

Channel 2<br />

Channel 3<br />

Channel 4<br />

Channel 5<br />

Channel 6<br />

Channel 7<br />

fCLK/2 0 to fCLK/2 15<br />

Selector<br />

Edge<br />

detection<br />

Figure 6-3. Block Diagram of Timer Array Unit 1<br />

PRS113 PRS112 PRS111 PRS110 PRS103 PRS102 PRS101 PRS100<br />

Selector<br />

4 4<br />

Prescaler<br />

Slave/master<br />

controller<br />

fCLK/2 0 to fCLK/2 15<br />

Selector<br />

Slave/master<br />

controller<br />

Trigger signal to slave channel<br />

Clock signal to slave channel<br />

Interrupt signal to slave channel<br />

Count clock<br />

selection<br />

Selector<br />

fMCK fTCLK<br />

Trigger<br />

selection<br />

CKS111<br />

Timer controller<br />

Mode<br />

selection<br />

CKS110 CCS11 MAS<br />

TER11 STS112<br />

TE17 TE16 TE15 TE14 TE13 TE12 TE11 TE10<br />

TS17 TS16 TS15 TS14 TS13 TS12 TS11 TS10<br />

TT17 TT16 TT15 TT14 TT13 TT12 TT11 TT10<br />

Timer output enable<br />

TOE17 TOE16 TOE15 TOE14 TOE13 TOE12 TOE11 TOE10<br />

register 1 (TOE1)<br />

TO17 TO16 TO15 TO14 TO13 TO12 TO11 TO10<br />

TOL17 TOL16 TOL15 TOL14 TOL13 TOL12 TOL11 TOL10<br />

Timer channel enable<br />

status register 1 (TE1)<br />

Timer channel start<br />

register 1 (TS1)<br />

Timer channel stop<br />

register 1 (TT1)<br />

Timer output<br />

register 1 (TO1)<br />

Timer output mode<br />

TOM17 TOM16 TOM15 TOM14 TOM13 TOM12 TOM11 TOM10<br />

register 1 (TOM1)<br />

Output<br />

controller<br />

Timer mode register 11 (TMR11)<br />

Interrupt<br />

controller<br />

Timer counter register 11 (TCR11)<br />

Timer data register 11 (TDR11)<br />

Timer status<br />

register 11 (TSR11)<br />

OVF<br />

Overflow 11<br />

STS111 STS110 CIS111 CIS110 MD113 MD112 MD111 MD110<br />

Note See Figure 6-4 for timer input pin selection and timer output pin selection.<br />

Timer output level<br />

register 1 (TOL1)<br />

R01UH0317EJ0004 Rev. 0.04 321<br />

Feb. 22, 2013<br />

TO10<br />

INTTM10<br />

TO11<br />

(timer output pin Note )<br />

INTTM11<br />

(timer interrupt)<br />

TO12<br />

INTTM12<br />

TO13<br />

INTTM13<br />

TO14<br />

INTTM14<br />

TO15<br />

INTTM15<br />

TO16<br />

INTTM16<br />

TO17<br />

INTTM17

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