RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission mode) SSmn STmn SEmn SDRmn SCKp pin SOp pin Shift register mn INTCSIp TSFmn Figure 12-54. Timing Chart of Slave Transmission (in Single-Transmission Mode) (Type 1: DAPmn = 0, CKPmn = 0) Transmit data 1 Transmit data 2 Transmit data 3 Transmit data 1 Shift operation Transmit data 2 Shift operation Transmit data 3 Shift operation Data transmission (8-bit length) Data transmission (8-bit length) Data transmission (8-bit length) Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 1), p: CSI number (p = 00, 01, 10) R01UH0317EJ0004 Rev. 0.04 625 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-55. Flowchart of Slave Transmission (in Single-Transmission Mode) Starting CSI communication Setting SAU1EN and SAU0EN bits of PER0 register to 1 Setting transfer rate by SPSm register SMRmn, SCRmn: Setting communication SDRmn[15:9]: Setting 0000000B SOm, SOEm: Setting output Port manipulation Writing 1 to SSmn bit Writing transmit data to SDRmn register Transfer end interrupt generated? Yes Transmission completed? Yes Writing 1 to STmn bit Clearing SAU1EN and SAU0EN bits of PER0 register to 0 End of communication Perform initial setting when SEmn = 0. Caution After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more clocks have elapsed. R01UH0317EJ0004 Rev. 0.04 626 Feb. 22, 2013 No No
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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12.5.3 Master transmission/receptio
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19.2 Configuration of DMA Controlle
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34.2 64-pin products 1276 R5F10CLDx
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