RL78/D1A User's Manual: Hardware - Renesas

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R01UH0317EJ0004 Rev. 0.04 1285 Feb. 22, 2013 Necessary WAIT I/O register(SFR) name R/W Bit R/W Address READ(MIN.) READ(MAX.) WRITE(MIN.) WRITE(MAX.) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1 8 16 7 6 5 4 3 2 1 0 1 1 1 1 F0116 SPS0 (Serial clock select register 0) - - E - - - - - - - - SPS0L - E - - - - - - - - - 1 1 1 1 F0118 SO0 (Serial output register 0) - - E - - - - - - - - 1 1 1 1 F011A 1 1 1 1 F0120 1 1 1 1 F0128 1 1 1 1 F0129 1 1 1 1 F0130 1 1 1 1 F0132 1 1 1 1 F0134 1 1 1 1 F0136 SOE0 (Serial output enabel register 0) - - E - - - - - - - - SOE0L E E - R R R R R R E E SOE0_1 SOE0_0 - - - - - - E E SOL0 (Serial output level register 0) - - E - - - - - - - - SOL0L - E - - - - - - - - - PLLSTS (PLL status register) R R - R R R R R R R R LOCK SELPLLS R - - - R - - - PLLCTL (PLL control register) E E - E E R E R E R E LCKSEL1 LCKSEL0 PLLDIV0 SELPLL PLLON E E - E - E - E SSR10 (Serial status register 10) - - R - - - - - - - - SSR10L - R - - - - - - - - - SSR11 (Serial status register 11) - - R - - - - - - - - SSR11L - R - - - - - - - - - SIR10 (Serial flag clear trigger register 10) - - E - - - - - - - - SIR10L - E - - - - - - - - - SIR11 (Serial flag clear trigger register 11) - - E - - - - - - - - SIR11L - E - - - - - - - - - 1 1 1 1 F0138 SMR10 (Serial mode register 10) - - E - - - - - - - - 1 1 1 1 F013A SMR11 (Serial mode register 11) - - E - - - - - - - - 1 1 1 1 F013C SCR10 (Serial communication operation setting register 10) - - E - - - - - - - - 1 1 1 1 F013E SCR11 (Serial communication operation setting register 11) - - E - - - - - - - - 1 1 1 1 F0140 SE1 (Serial channel enable status register 1) - - R - - - - - - - - SE1L R R - R R R R R R R R SE1_1 SE1_0 - - - - - - R R 1285 RL78/D1A APPENDIX A NUMBER OF WAIT CYCLES TO ACCESS I/O REGISTERS Specifications in this document are tentative and subject to change. Under development Preliminary document
R01UH0317EJ0004 Rev. 0.04 1286 Feb. 22, 2013 Necessary WAIT I/O register(SFR) name R/W Bit R/W Address READ(MIN.) READ(MAX.) WRITE(MIN.) WRITE(MAX.) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1 8 16 7 6 5 4 3 2 1 0 1 1 1 1 F0142 1 1 1 1 F0144 1 1 1 1 F0146 1 1 1 1 F0148 1 1 1 1 F014A 1 1 1 1 F0150 1 1 5 7 F0158 1 1 1 1 F015C 1 1 1 1 F015D 1 1 1 1 F015E 1 1 1 1 F015F 1 1 5 7 F0160 1 1 1 1 F0162 SS1 (Serial channel start trigger register 1) - - E - - - - - - - - SS1L E E - R R R R R R E E SS1_1 SS1_0 - - - - - - E E ST1 (Serial channel stop trigger register 1) - - E - - - - - - - - ST1L E E - R R R R R R E E ST1_1 ST1_0 - - - - - - E E SPS1 (Serial clock select register 1) - - E - - - - - - - - SPS1L - E - - - - - - - - - SO1 (Serial output register 1) - - E - - - - - - - - SO1L - E - - - - - - - - - SOE1 (Serial output enabel register 1) - - E - - - - - - - - SOE1L E E - R R R R R R E E SOE1_1 SOE1_0 - - - - - - E E SOL1 (Serial output level register 1) - - E - - - - - - - - SOL1L - E - - - - - - - - - MCMPC4 (Compare control register 4) E E - E E R E E E E E AOUT4 TWIN4 ZPD4 TEN4 ADB41 ADB40 DIR41 DIR40 E E R E E E E E ZPDS0 (ZPD detection voltage setting register0/ZPD analog input control) E E - E E E E E E E E ZPD2PC ZPD2S2 ZPD2S1 ZPD2S0 ZPD1PC ZPD1S2 ZPD1S1 ZPD1S0 E E E E E E E E ZPDS1 (ZPD detection voltage setting register1/ZPD analog input control) E E - E E E E E E E E ZPD4PC ZPD4S2 ZPD4S1 ZPD4S0 ZPD3PC ZPD3S2 ZPD3S1 ZPD3S0 E E E E E E E E CMPCTL (ZPD flag detection clock setting register) E E - R R R R E E E E DBCL3 DBCL2 DBCL1 DBCL0 - - - - E E E E ZPDEN (ZPD operation control register) E E - R R R R E E E E ZPD4EN ZPD3EN ZPD2EN ZPD1EN - - - - E E E E MCNTC0 (Compare control register 0) E E - E R E E E E E E CAE FULL PCE PCS SMCL2 SMCL1 SMCL0 E - E E E E E E MCMP1HW (Compare register 1HW) - - E - - - - - - - - MCMP10 (Compare register 10) - E - - - - - - - - - 1 1 1 1 F0163 MCMP11 (Compare register 11) - E - - - - - - - - - 1286 RL78/D1A APPENDIX A NUMBER OF WAIT CYCLES TO ACCESS I/O REGISTERS Specifications in this document are tentative and subject to change. Under development Preliminary document
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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12.5.3 Master transmission/receptio
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14.9.1 Message reception ..........
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19.2 Configuration of DMA Controlle
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28.1.1 Programming Environment.....
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RL78/D1A User's Manual: Hardware - Renesas

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