RL78/D1A User's Manual: Hardware - Renesas

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R01UH0317EJ0004 Rev. 0.04 1317 Feb. 22, 2013 Necessary WAIT I/O register(SFR) name R/W Bit R/W Address READ(MIN.) READ(MAX.) WRITE(MIN.) WRITE(MAX.) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1 8 16 7 6 5 4 3 2 1 0 - - - - FFF00 - - - - FFF01 - - - - FFF02 - - - - FFF03 - - - - FFF04 - - - - FFF05 - - - - FFF06 - - - - FFF07 - - - - FFF08 - - - - FFF09 - - - - FFF0C - - - - FFF0D - - - - FFF0E - - - - FFF0F - - - - FFF10 P0 (Port register 0) E E - E E E E E E E E P0_7 P0_6 P0_5 P0_4 P0_3 P0_2 P0_1 P0_0 E E E E E E E E P1 (Port register 1) E E - E E E E E E E E P1_7 P1_6 P1_5 P1_4 P1_3 P1_2 P1_1 P1_0 E E E E E E E E P2 (Port register 2) E E - E E E E E E E E P2_7 P2_6 P2_5 P2_4 P2_3 P2_2 P2_1 P2_0 E E E E E E E E P3 (Port register 3) E E - E E E E E E E E P3_7 P3_6 P3_5 P3_4 P3_3 P3_2 P3_1 P3_0 E E E E E E E E P4 (Port register 4) E E - R R R R R R R E P4_0 - - - - - - - E P5 (Port register 5) E E - E E E E E E E E P5_7 P5_6 P5_5 P5_4 P5_3 P5_2 P5_1 P5_0 E E E E E E E E P6 (Port register 6) E E - R E E E E E E E P6_6 P6_5 P6_4 P6_3 P6_2 P6_1 P6_0 - E E E E E E E P7 (Port register 7) E E - R R E E E E E E P7_5 P7_4 P7_3 P7_2 P7_1 P7_0 - - E E E E E E P8 (Port register 8) E E - E E E E E E E E P8_7 P8_6 P8_5 P8_4 P8_3 P8_2 P8_1 P8_0 E E E E E E E E P9 (Port register 9) E E - E E E E E E E E P9_7 P9_6 P9_5 P9_4 P9_3 P9_2 P9_1 P9_0 E E E E E E E E P12 (Port register 12) R R - R R R R R R R R P12_4 P12_3 P12_2 P12_1 - - - R R R R - P13 (Port register 13) E E - R E E E E E E E P13_7 P13_6 P13_5 P13_4 P13_3 P13_2 P13_1 P13_0 R E E E E E E E P14 (Port register 14) E E - R R R R R R R E P14_0 - - - - - - - E P15 (Port register 15) E E - R R R R R R R E P15_0 - - - - - - - E SDR00 (Serial data register 00) - - E - - - - - - - - SDR00L - E - - - - - - - - - 1317 RL78/D1A APPENDIX A NUMBER OF WAIT CYCLES TO ACCESS I/O REGISTERS Specifications in this document are tentative and subject to change. Under development Preliminary document
R01UH0317EJ0004 Rev. 0.04 1318 Feb. 22, 2013 Necessary WAIT I/O register(SFR) name R/W Bit R/W Address READ(MIN.) READ(MAX.) WRITE(MIN.) WRITE(MAX.) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1 8 16 7 6 5 4 3 2 1 0 - - - - FFF12 - - - - FFF14 - - - - FFF16 SDR01 (Serial data register 01) - - E - - - - - - - - SDR01L - E - - - - - - - - - SDR10 (Serial data register 10) - - E - - - - - - - - SDR10L - E - - - - - - - - - SDR11 (Serial data register 11) - - E - - - - - - - - SDR11L - E - - - - - - - - - - - - - FFF18 TDR00 (Timer data register 00 ) - - E - - - - - - - - - - - - FFF1A TDR01 (Timer data register 01) - - E - - - - - - - - - - - - FFF1E ADCR (10 bit A/D conversion result register) - - R - - - - - - - - - - - - FFF1F ADCRH (8 bit A/D conversion result register) - R - - - - - - - - - - - - - FFF20 - - - - FFF21 - - - - FFF22 - - - - FFF23 - - - - FFF24 - - - - FFF25 - - - - FFF26 - - - - FFF27 - - - - FFF28 - - - - FFF29 PM0 (Port mode register 0) E E - E E E E E E E E PM0_7 PM0_6 PM0_5 PM0_4 PM0_3 PM0_2 PM0_1 PM0_0 E E E E E E E E PM1 (Port mode register 1) E E - E E E E E E E E PM1_7 PM1_6 PM1_5 PM1_4 PM1_3 PM1_2 PM1_1 PM1_0 E E E E E E E E PM2 (Port mode register 2) E E - E E E E E E E E PM2_7 PM2_6 PM2_5 PM2_4 PM2_3 PM2_2 PM2_1 PM2_0 E E E E E E E E PM3 (Port mode register 3) E E - E E E E E E E E PM3_7 PM3_6 PM3_5 PM3_4 PM3_3 PM3_2 PM3_1 PM3_0 E E E E E E E E PM4 (Port mode register 4) E E - R R R R R R R E PM4_0 - - - - - - - E PM5 (Port mode register 5) E E - E E E E E E E E PM5_7 PM5_6 PM5_5 PM5_4 PM5_3 PM5_2 PM5_1 PM5_0 E E E E E E E E PM6 (Port mode register 6) E E - R E E E E E E E PM6_6 PM6_5 PM6_4 PM6_3 PM6_2 PM6_1 PM6_0 - E E E E E E E PM7 (Port mode register 7) E E - R R E E E E E E PM7_5 PM7_4 PM7_3 PM7_2 PM7_1 PM7_0 - - E E E E E E PM8 (Port mode register 8) E E - E E E E E E E E PM8_7 PM8_6 PM8_5 PM8_4 PM8_3 PM8_2 PM8_1 PM8_0 E E E E E E E E PM9 (Port mode register 9) E E - E E E E E E E E PM9_7 PM9_6 PM9_5 PM9_4 PM9_3 PM9_2 PM9_1 PM9_0 E E E E E E E E 1318 RL78/D1A APPENDIX A NUMBER OF WAIT CYCLES TO ACCESS I/O REGISTERS Specifications in this document are tentative and subject to change. Under development Preliminary document
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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12.5.3 Master transmission/receptio
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19.2 Configuration of DMA Controlle
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