RL78/D1A User's Manual: Hardware - Renesas

Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 14 CAN CONTROLLER
Table 14-19. Bit Configuration of Message Buffer Registers (2/2)
Address Symbol Bit 7/15 Bit 6/14 Bit 5/13 Bit 4/12 Bit 3/11 Bit 2/10 Bit 1/9 Bit 0/8
000F04x0H C1MDB01m Message data (byte 0)
000F04x1H
Message data (byte 1)
000F04x0H C1MDB0m Message data (byte 0)
000F04x1H C1MDB1m Message data (byte 1)
000F04x2H C1MDB23m Message data (byte 2)
000F04x3H Message data (byte 3)
000F04x2H C1MDB2m Message data (byte 2)
000F04x3H C1MDB3m Message data (byte 3)
000F04x4H C1MDB45m Message data (byte 4)
000F04x5H Message data (byte 5)
000F04x4H C1MDB4m Message data (byte 4)
000F04x5H C1MDB5m Message data (byte 5)
000F04x6H C1MDB67m Message data (byte 6)
000F04x7H Message data (byte 7)
000F04x6H C1MDB6m Message data (byte 6)
000F04x7H C1MDB7m Message data (byte 7)
000F04x8H C1MDLCm 0 0 0 0 MDLC3 MDLC2 MDLC1 MDLC0
000F04x9H C1MCONFm OWS RTR MT2 MT1 MT0 0 0 MA0
000F04xAH C1MIDLm
ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
000F04xBH
ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8
000F04xCH C1MIDHm
ID23 ID22 ID21 ID20 ID19 ID18 ID17 ID16
000F04xDH
IDE 0 0 ID28 ID27 ID26 ID25 ID24
000F04xEH C1MCTRLm (W) 0 0 0 Clear MOW Clear IE Clear DN Clear TRQ Clear RDY
000F04xFH
0 0 0 0 Set IE 0 Set TRQ Set RDY
000F04xEH C1MCTRLm (R) 0 0 0 MOW IE DN TRQ RDY
000F04xFH
0 0 MUC 0 0 0 0 0
Caution The actual register address is calculated as follows:
Register Address = Global Register Area Offset (CH dependent) + Offset Address as listed in table
above
Remarks 1. (R) When read
(W) When write
2. m = 0 to 15
3. x = 0 to F
R01UH0317EJ0004 Rev. 0.04 840
Feb. 22, 2013