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RL78/D1A User's Manual: Hardware - Renesas

RL78/D1A User's Manual: Hardware - Renesas

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Under development<br />

Preliminary document<br />

Specifications in this document are tentative and subject to change.<br />

<strong>RL78</strong>/<strong>D1A</strong> CHAPTER 11 A/D CONVERTER<br />

Figure 11-11. Format of Analog Input Channel Specification Register (ADS) (2/2)<br />

Address: FFF31H After reset: 00H R/W<br />

Symbol 7 6 5 4 3 2 1 0<br />

ADS 0 0 0 0 ADS3 ADS2 ADS1 ADS0<br />

Scan mode (ADMD = 1)<br />

ADS3 ADS2 ADS1 ADS0<br />

Analog input channel<br />

Scan 0 Scan 1 Scan 2 Scan 3<br />

0 0 0 0 ANI0 ANI1 ANI2 ANI3<br />

0 0 0 1 ANI1 ANI2 ANI3 ANI4<br />

0 0 1 0 ANI2 ANI3 ANI4 ANI5<br />

0 0 1 1 ANI3 ANI4 ANI5 ANI6<br />

0 1 0 0 ANI4 ANI5 ANI6 ANI7<br />

0 1 0 1 ANI5 ANI6 ANI7 ANI8<br />

Other than the above Setting prohibited<br />

Cautions 1. Be sure to clear bits 4, 5, 6, and 7 to 0.<br />

2. Set a channel to be used for A/D conversion in the input mode by using port mode registers 2, 15<br />

(PM2, PM15).<br />

3. Do not set the pin that is set by the A/D port configuration register (ADPC) as digital I/O by the<br />

ADS register.<br />

4. If using AVREFP as the + side reference voltage source of the A/D converter, do not select ANI0 as<br />

an A/D conversion channel.<br />

5. If using AVREFM as the side reference voltage source of the A/D converter, do not select ANI1 as<br />

an A/D conversion channel.<br />

6. Ignore the conversion result if the corresponding ANI pin does not exist in the product used.<br />

(8) Conversion result comparison upper limit setting register (ADUL)<br />

This register is used to specify the setting for checking the upper limit of the A/D conversion results.<br />

The A/D conversion results and ADUL register value are compared, and interrupt signal (INTAD) generation is<br />

controlled in the range specified for the ADCRK bit of A/D converter mode register 2 (ADM2) (shown in Figure 11-8).<br />

The ADUL register can be set by an 8-bit memory manipulation instruction.<br />

Reset signal generation sets this register to FFH.<br />

Caution When 10-bit resolution A/D conversion is selected, the higher eight bits of the 10-bit A/D conversion<br />

result register (ADCR) are compared with the ADUL register.<br />

Figure 11-12. Format of Conversion Result Comparison Upper Limit Setting Register (ADUL)<br />

Address: F0011H After reset: FFH R/W<br />

Symbol 7 6 5 4 3 2 1 0<br />

ADUL ADUL7 ADUL6 ADUL5 ADUL4 ADUL3 ADUL2 ADUL1 ADUL0<br />

R01UH0317EJ0004 Rev. 0.04 523<br />

Feb. 22, 2013

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