RL78/D1A User's Manual: Hardware - Renesas

Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF)
13.10 Dedicated Baud Rate Generator
The dedicated baud rate generator consists of a 3-bit prescaler block and a 12-bit programmable counter, and
generates a serial clock during transmission and reception with LIN-UARTn. Regarding the serial clock, a dedicated baud
rate generator output can be selected for each channel.
There is a 12-bit counter for transmission and another one for reception.
(1) Configuration of baud rate generator
fCLK
Figure 13-72. Configuration of Baud Rate Generator
UFnTXEn or UFnRXE bit
Prescaler
UFnCTL1:
UFnPRS2 to UFnPRS0
Prescaler
clock Note
(fUCLK)
UFnTXEn (or UFnRXE) bit
12-bit counter
Match detector 1/2 Baud rate
UFnCTL1:
UFnBRS11 to UFnBRS00
Note Clock that divides fCLK by 1, 2, 4, 8, 16, 32, 64, or 128
In automatic baud rate mode, the counter starts counting up when the LRxDn pin is low level and the UFnRXE bit is 1.
(a) Prescaler clock (fUCLK)
When the LINnEN bit of the PER register is “1”, a clock divided by a frequency division value specified by using
the UFnPRS2 to UFnPRS0 bits of the UFnCTL1 register is supplied to the 12-bit counter.
This clock is called the prescaler clock and its frequency is called fUCLK.
(b) Serial clock generation
A serial clock can be generated by setting the UFnCTL1 register.
The frequency division value for the 12-bit counter can be set by using the UFnBRS11 to UFnBRS00 bits of the
UFnCTL1 register.
Remark n = 0, 1
R01UH0317EJ0004 Rev. 0.04 772
Feb. 22, 2013