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RL78/D1A User's Manual: Hardware - Renesas

RL78/D1A User's Manual: Hardware - Renesas

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Under development<br />

Preliminary document<br />

Specifications in this document are tentative and subject to change.<br />

<strong>RL78</strong>/<strong>D1A</strong> CHAPTER 27 OPTION BYTE<br />

27.2 Format of User Option Byte<br />

The format of user option byte is shown below.<br />

Note 1<br />

Address: 000C0H/020C0H<br />

Figure 27-1. Format of User Option Byte (000C0H/020C0H)<br />

7 6 5 4 3 2 1 0<br />

WDTINT WINDOW1 WINDOW0 WDTON WDCS2 WDCS1 WDCS0 WDSTBYON<br />

WDTINT Use of interval interrupt of watchdog timer<br />

0 Interval interrupt is not used.<br />

1 Interval interrupt is generated when 75% +1/2fIL of the overflow time is reached.<br />

Note 2<br />

WINDOW1 WINDOW0 Watchdog timer window open period<br />

0 0 Setting prohibited<br />

0 1 50%<br />

1 0 75%<br />

1 1 100%<br />

WDTON Operation control of watchdog timer counter<br />

0 Counter operation disabled (counting stopped after reset)<br />

1 Counter operation enabled (counting started after reset)<br />

WDCS2 WDCS1 WDCS0 Watchdog timer overflow time<br />

(fIL = 17.25 kHz (MAX.))<br />

0 0 0 2 6 /fIL (3.71 ms)<br />

0 0 1 2 7 /fIL (7.42 ms)<br />

0 1 0 2 8 /fIL (14.84 ms)<br />

0 1 1 2 9 /fIL (29.68 ms)<br />

1 0 0 2 11 /fIL (118.72 ms)<br />

1 0 1 2 13 /fIL (474.90 ms)<br />

1 1 0 2 14 /fIL (949.80 ms)<br />

1 1 1 2 16 /fIL (3799.19m s)<br />

WDSTBYON Operation control of watchdog timer counter (HALT/STOP mode)<br />

Note 2<br />

0 Counter operation stopped in HALT/STOP mode<br />

1 Counter operation enabled in HALT/STOP mode<br />

Notes 1. Set the same value as 000C0H to 020C0H when the boot swap operation is used because 000C0H is<br />

replaced by 020C0H.<br />

2. The window open period is 100% when WDSTBYON = 0, regardless the value of the WINDOW1 and<br />

WINDOW0 bits.<br />

Caution The watchdog timer continues its operation during EEPROM emulation. During processing, the<br />

interrupt acknowledge time is delayed. Set the overflow time and window size taking this delay into<br />

consideration.<br />

Remark fIL: Low-speed on-chip oscillator clock frequency<br />

R01UH0317EJ0004 Rev. 0.04 1154<br />

Feb. 22, 2013

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