RL78/D1A User's Manual: Hardware - Renesas

Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 5 CLOCK GENERATOR
CHAPTER 5 CLOCK GENERATOR
The presence or absence of connecting resonator pin for main system clock, connecting resonator pin for subsystem
clock, external clock input pin for main system clock, and external clock input pin for subsystem clock, depends on the
product.
Output pin 100-pin 80-pin 64-pin 48-pin
X1, X2 pins
EXCLK pin
XT1, XT2 pins N/A
5.1 Functions of Clock Generator
The clock generator generates the clock to be supplied to the CPU and peripheral hardware.
The following three kinds of system clocks and clock oscillators are selectable.
(1) Main system clock
X1 oscillator
This circuit oscillates a clock of fX = 1 to 20 MHz by connecting a resonator to X1 and X2.
Oscillation can be stopped by executing the STOP instruction or setting of the MSTOP bit (bit 7 of the clock
operation status control register (CSC)).
High-speed on-chip oscillator
The frequency at which to oscillate can be selected from among fIH = 32, 24, 16, 8, or 4 MHz (typ.) by using
the option byte (000C2H). After a reset release, the CPU always starts operating with this High-speed onchip
oscillator clock. Oscillation can be stopped by executing the STOP instruction or setting the HIOSTOP
bit (bit 0 of the CSC register).
The frequency specified by using an option byte can be changed by using the high-speed on-chip oscillator
frequency select register (HOCODIV). For details about the frequency, see Figure 5-9 Format of High-speed
On-chip Oscillator Frequency Select Register (HOCODIV).
The frequencies that can be specified for the high-speed on-chip oscillator by using the option byte and the
high-speed on-chip oscillator frequency select register (HOCODIV) are shown in CHAPTER 32 ELECTRICAL
SPECIFICATIONS (J GRADE PRODUCT) (TARGET) and CHAPTER 33 ELECTRICAL SPECIFICATIONS
(L GRADE PRODUCT) (TARGET).
An external main system clock (fEX = 1 to 20 MHz) can also be supplied from the EXCLK/X2/P122 pin. An external
main system clock input can be disabled by executing the STOP instruction or setting of the MSTOP bit.
As the main system clock, a high-speed system clock (X1 clock or external main system clock) or high-speed onchip
oscillator clock can be selected by setting of the MCM0 bit (bit 4 of the system clock control register (CKC)).
(2) PLL clock
A clock that is the main system clock multiplied by 1, 6 or 8 can be oscillated. Oscillation can be stopped by
executing a STOP instruction or by setting PLLON (bit 0 of PLLCTL) to 0.
(3) Subsystem clock
XT1 clock oscillator
This circuit oscillates a clock of fXT = 32.768 kHz by connecting a 32.768 kHz resonator to XT1 and XT2.
Oscillation can be stopped by setting the XTSTOP bit (bit 6 of the clock operation status control register (CSC)).
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