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RL78/D1A User's Manual: Hardware - Renesas

RL78/D1A User's Manual: Hardware - Renesas

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Under development<br />

Preliminary document<br />

Specifications in this document are tentative and subject to change.<br />

<strong>RL78</strong>/<strong>D1A</strong> CHAPTER 28 FLASH MEMORY<br />

28.1.1 Programming Environment<br />

The environment required for writing a program to the flash memory of the <strong>RL78</strong>/<strong>D1A</strong> is illustrated below.<br />

Host machine<br />

Figure 28-1. Environment for Writing Program to Flash Memory<br />

PG-FP5, FL-PR5 E1<br />

VDD/EVDD/SMVDD<br />

RS-232C<br />

VSS/EVSS/SMVSS<br />

USB<br />

RESET<br />

Dedicated flash TOOL0 (dedicated single-line UART)<br />

memory programmer<br />

<strong>RL78</strong>/<strong>D1A</strong><br />

A host machine that controls the dedicated flash memory programmer is necessary.<br />

To interface between the dedicated flash memory programmer and the <strong>RL78</strong>/<strong>D1A</strong>, the TOOL0 pin is used for<br />

manipulation such as writing and erasing via a dedicated single-line UART.<br />

28.1.2 Communication Mode<br />

Communication between the dedicated flash memory programmer and the <strong>RL78</strong>/<strong>D1A</strong> is established by serial<br />

communication using the TOOL0 pin via a dedicated single-line UART of the <strong>RL78</strong>/<strong>D1A</strong>.<br />

Transfer rate: 1 M, 500 k, 250 k, 115.2 kbps<br />

Figure 28-2. Communication with Dedicated Flash Memory Programmer<br />

PG-FP5, FL-PR5<br />

E1<br />

Dedicated flash<br />

memory programmer<br />

VDD<br />

EMVDD<br />

GND<br />

RESETNote 1 ,<br />

Note 2<br />

/RESET<br />

Note 1<br />

TOOL0<br />

Note 2<br />

SI/RxD<br />

VDD/EVDD/SMVDD<br />

R01UH0317EJ0004 Rev. 0.04 1163<br />

Feb. 22, 2013<br />

EVDD<br />

Note 3<br />

VSS/EVSS/SMVSS/REGC<br />

RESET<br />

TOOL0<br />

Notes 1. When using E1 on-chip debugging emulator.<br />

2. When using PG-FP5 or FL-PR5.<br />

3. Connect REGC pin to ground via a capacitor (default: 0.47 F).<br />

Caution Make EVDD, SMVDD the same potential as VDD.<br />

<strong>RL78</strong>/<strong>D1A</strong>

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