RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 12 SERIAL ARRAY UNIT (2) Operation procedure Figure 12-73. Initial Setting Procedure for Address Field Transmission Starting initial setting Setting PER01 and PER1 registers Setting SPSm register Setting SMRmn register Setting SCRmn register Setting SDRmn register Setting SOm register Setting port Setting SOm register Wait Setting SOm register Changing setting of SOEm register Writing to SSm register Starting communication Release the serial array unit from the reset status and start clock supply. Set the operation clock. Set an operation mode, etc. Set a communication format. Set a transfer baud rate. Manipulate the SOmn and CKO0mn bits and set an initial output level. Enable data output, clock output, and the N-ch open-drain output (VDD tolerance) mode of the target channel by setting a port register, a port mode register, and a port output mode register. Clear the SOmn bit to 0 to generate the start condition. Secure a wait time so that the specifications of I 2 C on the slave side are satisfied. Clear the CKOmn bit to 0 to lower the clock output level. Set the SOEmn bit to 1 and enable data output of the target channel. Set the SSmn bit of the target channel to 1 to set SEmn = 1. Set address and R/W to the SDRmn register and start communication. Caution After setting the PER0 registers to 1, be sure to set the SPSm register after 4 or more clocks have elapsed. Remark m: Unit number (m = 1), n: Channel number (n = 1), r: IIC number (r = 11) R01UH0317EJ0004 Rev. 0.04 653 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow SSmn SEmn SOEmn SDRmn SCLr output SDAr output SDAr input Shift register mn INTIICr TSFmn Figure 12-74. Timing Chart of Address Field Transmission CKOmn bit manipulation SOmn bit manipulation D7 D6 Address field transmission D5 D4 D3 D2 D1 D0 Address R/W D7 D6 D5 D4 D3 D2 D1 D0 R01UH0317EJ0004 Rev. 0.04 654 Feb. 22, 2013 Shift operation Remark m: Unit number (m = 1), n: Channel number (n = 1), r: IIC number (r = 11) ACK
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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12.5.3 Master transmission/receptio
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19.2 Configuration of DMA Controlle
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34.2 64-pin products 1276 R5F10CLDx
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34.4 100-pin products 1278 CHAPTER
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RL78/D1A User’s Manual: Hardware
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