RL78/D1A User's Manual: Hardware - Renesas

Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 5 CLOCK GENERATOR
Remark fX: X1 clock oscillation frequency
fIH: High-speed on-chip oscillator clock frequency
fEX: External main system clock frequency
fMX: High-speed system clock frequency
fMAIN: Main system clock frequency
fXT: XT1 clock oscillation frequency
fSUB: Subsystem clock frequency
fCLK: CPU/peripheral hardware clock frequency
fIL: Low-speed on-chip oscillator clock frequency
PLL control register
(PLLCTL)
PLL status register
(PLLSTS)
SELPLLS
Remark fMAIN: Main system clock
fIL: Low-speed on-chip oscillator clock
fPLLI: PLL input clock
fPLLO: PLL output clock
fPLL: PLL clock
fMP: PLL output for main system clock
Figure 5-2. Block Diagram of PLL Circuit
Option byte
(000C1H)
PLL control register
(PLLCTL)
PLL control register
(PLLCTL)
PLL status register
(PLLSTS)
PLL control register
(PLLCTL)
LCKSEL0 LCKSEL1 GDPLL SELPLL
GDPLL PLLON OPTPLL GDPLL PLLDIV0
PLL circuit
(X12, X16)
Divider
(2 1 , 2 2 )
fPLLI fPLLO fPLL fMP
Clock monitor controller
Counter LOCK
CSS CLKMB
System clock control
register (CKC)
Selector
Prescaler
Clock output
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Feb. 22, 2013