RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 11 A/D CONVERTER (1) Peripheral enable register 1 (PER1) This register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise. When the A/D converter is used, be sure to set bit 7 (ADCEN) of this register to 1. The PER1 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Address: F00F1H After reset: 00H R/W Figure 11-2. Format of Peripheral Enable Register 1 (PER1) Symbol PER1 ADCEN 0 MTRCEN SGEN 0 0 0 0 ADCEN Control of A/D converter input clock supply 0 Stops input clock supply. SFR used by the A/D converter cannot be written. The A/D converter is in the reset status. 1 Enables input clock supply. SFR used by the A/D converter can be read/written. Cautions When setting the A/D converter, be sure to set the ADCEN bit to 1 first. If ADCEN = 0, writing to a control register of the A/D converter is ignored, and, even if the register is read, only the default value is read (except for port mode registers 2 and 15 (PM2, PM15) and A/D port configuration register (ADPC)). R01UH0317EJ0004 Rev. 0.04 509 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 11 A/D CONVERTER (2) A/D converter mode register 0 (ADM0) This register sets the conversion time for analog input to be A/D converted, and starts/stops conversion. The ADM0 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Address: FFF30H After reset: 00H R/W Figure 11-3. Format of A/D Converter Mode Register 0 (ADM0) Symbol 6 5 4 3 2 1 ADM0 ADCS ADMD FR2 Note 1 FR1 Note 1 FR0 Note 1 LV1 Note 1 LV0 Note 1 ADCE ADCS A/D conversion operation control 0 Stops conversion operation [When read] Conversion stopped/standby status 1 Enables conversion operation [When read] While in the software trigger mode: Conversion operation status While in the hardware trigger wait mode: Stabilization wait status + conversion operation status ADMD Specification of the A/D conversion channel selection mode 0 Select mode 1 Scan mode Note 2 ADCE A/D voltage comparator operation control 0 Stops A/D voltage comparator operation 1 Enables A/D voltage comparator operation Notes 1. For details of the FR2 to FR0, LV1, LV0 bits, and A/D conversion, see Table 11-3 A/D Conversion Time Selection. 2. While in the software trigger mode or hardware trigger no-wait mode, the operation of the A/D voltage comparator is controlled by the ADCS and ADCE bits, and it takes 1 s from the start of operation for the operation to stabilize. Therefore, when the ADCS bit is set to 1 after 1 s or more has elapsed from the time ADCE bit is set to 1, the conversion result at that time has priority over the first conversion result. Otherwise, ignore data of the first conversion. Cautions 1. Change the ADMD, FR2 to FR0, LV1, LV0, and ADCE bits while conversion is stopped or on standby (ADCS = 0). 2. Do not change the ADCE and ADCS bits from 0 to 1 at the same time by using an 8-bit manipulation instruction. Be sure to set these bits in the order described in 11.7 A/D Converter Setup Flowchart. R01UH0317EJ0004 Rev. 0.04 510 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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34.2 64-pin products 1276 R5F10CLDx
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RL78/D1A User’s Manual: Hardware
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