RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 5 CLOCK GENERATOR Table 5-5. CPU Clock Transition and SFR Register Setting Examples (5/6) (9) CPU clock changing from subsystem clock (D) to high-speed system clock (C) (Setting sequence of SFR registers) Setting Flag of SFR Register Status Transition (D) (C) (X1 clock: 1 MHz fX 10 MHz) (D) (C) (X1 clock: 10 MHz < fX 20 MHz) (D) (C) (external main clock) OSTS Register CSC Register OSTC Register CKC Register MSTOP MCM0 CSS Note 0 Must be checked 1 0 Note 0 Must be checked 1 0 Note 0 Must not be checked 1 0 Unnecessary if the CPU is operating with the high-speed system clock Unnecessary if these registers are already set Note Set the oscillation stabilization time as follows. Desired the oscillation stabilization time counter status register (OSTC) oscillation stabilization time Oscillation stabilization time set by the oscillation stabilization time select register (OSTS) Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see CHAPTER 32 ELECTRICAL SPECIFICATIONS (J GRADE PRODUCT) (TARGET) and CHAPTER 33 ELECTRICAL SPECIFICATIONS (L GRADE PRODUCT) (TARGET). (10) HALT mode (E) set while CPU is operating with high-speed on-chip oscillator clock (B) HALT mode (F) set while CPU is operating with high-speed system clock (C) HALT mode (G) set while CPU is operating with subsystem clock (D) (B) (E) (C) (F) (D) (G) Status Transition Setting Executing HALT instruction Remark (A) to (J) in Table 5-5 correspond to (A) to (J) in Figure 5-20. R01UH0317EJ0004 Rev. 0.04 307 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 5 CLOCK GENERATOR Table 5-5. CPU Clock Transition and SFR Register Setting Examples (6/6) (11) STOP mode (H) set while CPU is operating with high-speed on-chip oscillator clock (B) STOP mode (I) set while CPU is operating with high-speed system clock (C) (B) (H) (C) (I) (Setting sequence) Status Transition Setting Stopping peripheral functions that cannot In X1 oscillation operate in STOP mode Sets the OSTS register External main system clock (12) CPU changing from STOP mode (H) to SNOOZE mode (J) R01UH0317EJ0004 Rev. 0.04 308 Feb. 22, 2013 Executing STOP instruction For details about the setting for switching from the STOP mode to the SNOOZE mode, see 11.8 SNOOZE Mode Function, 12.5.7 SNOOZE mode function and 12.6.3 SNOOZE mode function. Remark (A) to (J) in Table 5-5 correspond to (A) to (J) in Figure 5-20.
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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34.2 64-pin products 1276 R5F10CLDx
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RL78/D1A User’s Manual: Hardware
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