RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 11 A/D CONVERTER Figure 11-8. ADRCK Bit Interrupt Signal Generation Range ADCR register value (A/D conversion result) 1111111111 0000000000 (ADUL < ADCR) (ADLL ≤ ADCR ≤ ADUL) (ADCR < ADLL) INTAD is generated when ADRCK = 1. INTAD is generated when ADRCK = 0. INTAD is generated when ADRCK = 1. ADUL register setting ADLL register setting Remark If INTAD does not occur, the A/D conversion result is not stored in the ADCR or ADCRH register. (5) 10-bit A/D conversion result register (ADCR) This register is a 16-bit register that stores the A/D conversion result in the select mode. The lower 6 bits are fixed to 0. Each time A/D conversion ends, the conversion result is loaded from the successive approximation register (SAR). The higher 8 bits of the conversion result are stored in FFF1FH and the lower 2 bits are stored in the higher 2 bits of FFF1EH. Note The ADCR register can be read by a 16-bit memory manipulation instruction. Reset signal generation clears this register to 0000H. Note If the A/D conversion result is outside the range specified by using the A/D conversion comparison function (the value specified by the ADRCK bit of the ADM2 register and ADUL/ADLL registers; see Figure 11-8), the result is not stored. Symbol ADCR Figure 11-9. Format of 10-bit A/D Conversion Result Register (ADCR) Address: FFF1FH, FFF1EH After reset: 0000H R FFF1FH FFF1EH Cautions 1. When writing to the A/D converter mode register 0 (ADM0), analog input channel specification register (ADS), and A/D port configuration register (ADPC), the contents of the ADCR register may become undefined. Read the conversion result following conversion completion before writing to the ADM0, ADS, and ADPC registers. Using timing other than the above may cause an incorrect conversion result to be read. 2. When 8-bit resolution A/D conversion is selected (when the ADTYP bit of A/D converter mode register 2 (ADM2) is 1) and the ADCR register is read, 0 is read from the lower two bits (ADCR1 and ADCR0). 3. When the ADCR register is accessed in 16-bit units, the higher 10 bits of the conversion result are read in order starting at bit 15. R01UH0317EJ0004 Rev. 0.04 521 Feb. 22, 2013 0 0 0 0 0 0
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 11 A/D CONVERTER (6) 8-bit A/D conversion result register (ADCRH) This register is an 8-bit register that stores the A/D conversion result. The higher 8 bits of 10-bit resolution are stored. The ADCRH register can be read by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Note If the A/D conversion result is outside the range specified by using the A/D conversion comparison function (the value specified by the ADRCK bit of the ADM2 register and ADUL/ADLL registers; see Figure 11-8), the result is not stored. Figure 11-10. Format of 8-bit A/D Conversion Result Register (ADCRH) Address: FFF1FH After reset: 00H R Symbol ADCRH 7 6 5 4 3 2 1 0 Caution When writing to the A/D converter mode register 0 (ADM0), analog input channel specification register (ADS), and A/D port configuration register (ADPC), the contents of the ADCRH register may become undefined. Read the conversion result following conversion completion before writing to the ADM0, ADS, and ADPC registers. Using timing other than the above may cause an incorrect conversion result to be read. (7) Analog input channel specification register (ADS) This register specifies the input channel of the analog voltage to be A/D converted. The ADS register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 11-11. Format of Analog Input Channel Specification Register (ADS) (1/2) Address: FFF31H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 ADS 0 0 0 0 ADS3 ADS2 ADS1 ADS0 Select mode (ADMD = 0) ADS3 ADS2 ADS1 ADS0 Analog input channel Input source 0 0 0 0 ANI0 P20/ANI0/AVREFP pin 0 0 0 1 ANI1 P21/ANI1/AVREFM pin 0 0 1 0 ANI2 P22/ANI2 pin 0 0 1 1 ANI3 P23/ANI3 pin 0 1 0 0 ANI4 P24/ANI4 pin 0 1 0 1 ANI5 P25/ANI5 pin 0 1 1 0 ANI6 P26/ANI6 pin 0 1 1 1 ANI7 P27/ANI7 pin 1 0 0 0 ANI8 P150/ANI8 pin Other than the above Setting prohibited R01UH0317EJ0004 Rev. 0.04 522 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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6.8 Operation of Plural Channels of
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RL78/D1A User’s Manual: Hardware
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