RL78/D1A User's Manual: Hardware - Renesas

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R01UH0317EJ0004 Rev. 0.04 1287 Feb. 22, 2013 Necessary WAIT I/O register(SFR) name R/W Bit R/W Address READ(MIN.) READ(MAX.) WRITE(MIN.) WRITE(MAX.) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1 8 16 7 6 5 4 3 2 1 0 1 1 1 1 F0164 MCMP2HW (Compare register 2HW) - - E - - - - - - - - MCMP20 (Compare register 20) - E - - - - - - - - - 1 1 1 1 F0165 MCMP21 (Compare register 21) - E - - - - - - - - - 1 1 1 1 F0166 MCMP3HW (Compare register 3HW) - - E - - - - - - - - MCMP30 (Compare register 30) - E - - - - - - - - - 1 1 1 1 F0167 MCMP31 (Compare register 31) - E - - - - - - - - - 1 1 1 1 F0168 MCMP4HW (Compare register 4HW) - - E - - - - - - - - MCMP40 (Compare register 40) - E - - - - - - - - - 1 1 1 1 F0169 MCMP41 (Compare register 41) - E - - - - - - - - - 1 1 5 7 F016A 1 1 5 7 F016C 1 1 5 7 F016E MCMPC1 (Compare control register 1) E E - E E R E E E E E AOUT1 TWIN1 ZPD1 TEN1 ADB11 ADB10 DIR11 DIR10 E E R E E E E E MCMPC2 (Compare control register 2) E E - E E R E E E E E AOUT2 TWIN2 ZPD2 TEN2 ADB21 ADB20 DIR21 DIR20 E E R E E E E E MCMPC3 (Compare control register 3) E E - E E R E E E E E AOUT3 TWIN3 ZPD3 TEN3 ADB31 ADB30 DIR31 DIR30 E E R E E E E E 1 1 1 1 F0170 DSA2 (DMA SFR address register 2) - E - - - - - - - - - 1 1 1 1 F0171 DSA3 (DMA SFR address register 3) - E - - - - - - - - - 1 1 1 1 F0172 DRA2 (DMA RAM address register 2) - - E - - - - - - - - DRA2L (DMA RAM address register 2L) - E - - - - - - - - - 1 1 1 1 F0173 DRA2H (DMA RAM address register 2H) - E - - - - - - - - - 1 1 1 1 F0174 DRA3 (DMA RAM address register 3) - - E - - - - - - - - DRA3L (DMA RAM address register 3L) - E - - - - - - - - - 1 1 1 1 F0175 DRA3H (DMA RAM address register 3H) - E - - - - - - - - - 1 1 1 1 F0176 DBC2 (DMA byte count register 2) - - E - - - - - - - - DBC2L (DMA byte count register 2L) - E - - - - - - - - - 1 1 1 1 F0177 DBC2H (DMA byte count register 2H) - E - - - - - - - - - 1 1 1 1 F0178 DBC3 (DMA byte count register 3) - - E - - - - - - - - DBC3L (DMA byte count register 3L) - E - - - - - - - - - 1 1 1 1 F0179 DBC3H (DMA byte count register 3H) - E - - - - - - - - - 1 1 1 1 F017A DMC2 (DMA mode control register 2) E E - E E E E E E E E STG2 DRS2 DS2 DWAIT2 IFC23 IFC22 IFC21 IFC20 E E E E E E E E 1287 RL78/D1A APPENDIX A NUMBER OF WAIT CYCLES TO ACCESS I/O REGISTERS Specifications in this document are tentative and subject to change. Under development Preliminary document
R01UH0317EJ0004 Rev. 0.04 1288 Feb. 22, 2013 Necessary WAIT I/O register(SFR) name R/W Bit R/W Address READ(MIN.) READ(MAX.) WRITE(MIN.) WRITE(MAX.) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1 8 16 7 6 5 4 3 2 1 0 1 1 1 1 F017B 1 1 1 1 F017C 1 1 1 1 F017D 1 1 1 1 F017F DMC3 (DMA mode control register 3) E E - E E E E E E E E STG3 DRS3 DS3 DWAIT3 IFC33 IFC32 IFC31 IFC30 E E E E E E E E DRC2 (DMA operation control register 2) E E - E R R R R R R E DEN2 DST2 E - - - - - - E DRC3 (DMA operation control register 3) E E - E R R R R R R E DEN3 DST3 E - - - - - - E DWAITALL (DMA all-channel forced wait register) E E - E R R R R R R E PRVARI DWAITALL0 E - - - - - - E - - - - F0180 TCR00 (Timer counter register 00) - - R - - - - - - - - - - - - F0182 TCR01 (Timer counter register 01) - - R - - - - - - - - - - - - F0184 TCR02 (Timer counter register 02) - - R - - - - - - - - - - - - F0186 TCR03 (Timer counter register 03) - - R - - - - - - - - - - - - F0188 TCR04 (Timer counter register 04) - - R - - - - - - - - - - - - F018A TCR05 (Timer counter register 05) - - R - - - - - - - - - - - - F018C TCR06 (Timer counter register 06) - - R - - - - - - - - - - - - F018E TCR07 (Timer counter register 07) - - R - - - - - - - - - - - - F0190 TMR00 (Timer mode register 00) - - E - - - - - - - - - - - - F0192 TMR01 (Timer mode register 01) - - E - - - - - - - - - - - - F0194 TMR02 (Timer mode register 02) - - E - - - - - - - - - - - - F0196 TMR03 (Timer mode register 03) - - E - - - - - - - - - - - - F0198 TMR04 (Timer mode register 04) - - E - - - - - - - - - - - - F019A TMR05 (Timer mode register 05) - - E - - - - - - - - - - - - F019C TMR06 (Timer mode register 06) - - E - - - - - - - - - - - - F019E TMR07 (Timer mode register 07) - - E - - - - - - - - - - - - F01A0 - - - - F01A2 - - - - F01A4 TSR00 (Timer status register 00) - - R - - - - - - - - TSR00L - R - - - - - - - - - TSR01 (Timer status register 01) - - R - - - - - - - - TSR01L - R - - - - - - - - - TSR02 (Timer status register 02) - - R - - - - - - - - TSR02L - R - - - - - - - - - 1288 RL78/D1A APPENDIX A NUMBER OF WAIT CYCLES TO ACCESS I/O REGISTERS Specifications in this document are tentative and subject to change. Under development Preliminary document
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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12.5.3 Master transmission/receptio
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19.2 Configuration of DMA Controlle
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RL78/D1A User's Manual: Hardware - Renesas

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