RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-10. Format of Timer Clock Select Register m (TPSm) Address: F01B6H, F01B7H (TPS0), F01F6H, F01F7H (TPS1) After reset: 0000H R/W F0236H, F0237H (TPS2) Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TPSm PRS m33 PRS mk3 PRS mk2 PRS m32 PRS mk1 PRS m31 PRS mk0 PRS m30 PRS m23 PRS m22 PRS m21 fCLK = 2 MHz PRS m20 R01UH0317EJ0004 Rev. 0.04 331 Feb. 22, 2013 PRS m13 PRS m12 PRS m11 PRS m10 Selection of operation clock (CKmk) Note fCLK = 8 MHz fCLK = 16 MHz PRS m03 fCLK = 24 MHz PRS m02 PRS m01 fCLK = 32 MHz 0 0 0 0 fCLK 2 MHz 8 MHz 16 MHz 24 MHz 32 MHz 0 0 0 1 fCLK/2 1 MHz 4 MHz 8 MHz 12 MHz 16 MHz 0 0 1 0 fCLK/2 2 500 kHz 2 MHz 4 MHz 6 MHz 8 MHz 0 0 1 1 fCLK/2 3 250 kHz 1 MHz 2 MHz 3 MHz 4 MHz 0 1 0 0 fCLK/2 4 125 kHz 0.5 MHz 1 MHz 1.5 MHz 2 MHz 0 1 0 1 fCLK/2 5 62.5 kHz 250 kHz 0.5 MHz 750 kHz 1 MHz 0 1 1 0 fCLK/2 6 31.25 kHz 125 kHz 250 kHz 375 kHz 500 kHz 0 1 1 1 fCLK/2 7 15.63 kHz 62.5 kHz 125 kHz 187.5 kHz 250 kHz 1 0 0 0 fCLK/2 8 7.81 kHz 31.25 kHz 62.5 kHz 93.75 kHz 125 kHz 1 0 0 1 fCLK/2 9 3.91 kHz 15.63 kHz 31.25 kHz 46.87 kHz 62.5 kHz 1 0 1 0 fCLK/2 10 1.95 kHz 7.81 kHz 15.63 kHz 23.43 kHz 31.25 kHz 1 0 1 1 fCLK/2 11 976 Hz 3.91 kHz 7.81 kHz 11.71 kHz 15.63 kHz 1 1 0 0 fCLK/2 12 488 Hz 1.95 kHz 3.91 kHz 5.85 kHz 7.81 kHz 1 1 0 1 fCLK/2 13 244 Hz 976 Hz 1.95 kHz 2.92 kHz 3.91 kHz 1 1 1 0 fCLK/2 14 122 Hz 488 Hz 976 Hz 1.46 kHz 1.95 kHz 1 1 1 1 fCLK/2 15 61 Hz 244 Hz 488 Hz 732.42 Hz 976 Hz Note When changing the clock selected for fCLK (by changing the system clock control register (CKC) value), stop the timer array unit (TTm = 00FFH). The timer array unit must also be stopped if the operating clock specified by using the CKSmn bit (fMCK), or the valid edge of the signal input from the TImn pin is selected as the count clock (fTCLK). Remark m: Unit number (m = 0 to 2) n: Channel number (n = 0 to 7) k = 0 to 3 PRS m00
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 6 TIMER ARRAY UNIT (3) Timer mode register mn (TMRmn) TMRmn sets an operation mode of channel n. It is used to select an operation clock (fMCK), a count clock, whether the timer operates as the master or a slave, a start trigger and a capture trigger, the valid edge of the timer input, and an operation mode (interval, capture, event counter, one-count, or capture & one-count). Rewriting TMRmn is prohibited when the register is in operation (when TEm = 1). However, bits 7 and 6 (CISmn1, CISmn0) can be rewritten even while the register is operating with some functions (when TEm = 1) (for details, see 6.7 Operation of Timer Array Unit as Independent Channel and 6.8 Operation of Plural Channels of Timer Array Unit). TMRmn can be set by a 16-bit memory manipulation instruction. Reset signal generation clears this register to 0000H. Figure 6-11. Format of Timer Mode Register mn (TMRmn) (1/3) Address: F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07), After reset: 0000H R/W F01D0H, F01D1H (TMR10) to F01DEH, F01DFH (TMR17), F0210H, F0211H (TMR20) to F021EH, F021FH (TMR27) Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TMRmn CKS mn1 CKS mn1 CKS mn0 CKS mn0 0 CCS mn0 MAST ERmn STS mn2 STS mn1 STS mn0 0 0 Operation clock CKm0 set byTPSm register 0 1 Operation clock CKm1 set by TPSm register 1 0 Operation clock CKm2 set by TPSm register 1 1 Operation clock CKm3 set by TPSm register R01UH0317EJ0004 Rev. 0.04 332 Feb. 22, 2013 CIS mn1 CIS mn0 0 0 MD mn3 Selection of operation clock (fMCK) of channel n Operation clock (fMCK) is used by the edge detector. A count clock (fTCLK) is generated depending on the setting of the CCSmn bit. CCS mn0 0 Operation clock (fMCK) specified by CKSmn bit 1 Valid edge of input signal input from TImn pin Selection of count clock (fTCLK) of channel n Count clock (fTCLK) is used for the timer counter, output controller, and interrupt controller. Cautions 1. Be sure to clear bits 13, 5, and 4 to “0”. 2. The timer array unit must be stopped (TTm = 00FFH) if the clock selected for fCLK is changed (by changing the value of the system clock control register (CKC)), even if the operating clock specified by using the CKSmn bit (fMCK), or the valid edge of the signal input from the TImn pin is selected as the count clock (fTCLK). Remark m: Unit number (m = 0 to 2) n: Channel number (n = 0 to 7) MD mn2 MD mn1 MD mn0
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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RL78/D1A User’s Manual: Hardware
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