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RL78/D1A User's Manual: Hardware - Renesas

RL78/D1A User's Manual: Hardware - Renesas

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Under development<br />

Preliminary document<br />

Specifications in this document are tentative and subject to change.<br />

<strong>RL78</strong>/<strong>D1A</strong> CHAPTER 14 CAN CONTROLLER<br />

Figure 14-50. Format of CAN Message Control Register m (C0MCTRLm, C1MCTRLm) (3/3)<br />

Set TRQ Clear TRQ Setting of TRQ Bit<br />

0 1 TRQ bit is cleared to 0.<br />

1 0 TRQ bit is set to 1.<br />

Other than above TRQ bit is not changed.<br />

Caution While receiving a message from another node or transmitting the messages, there<br />

is a possibility of not to begin immediately the transmission even if the TRQ bit is<br />

set to 1.<br />

The transmission is not aborted even if the TRQ bit is cleared to 0. The<br />

transmission is continued if a message is currently being transmitted and until the<br />

transmission is completed (successfully or not).<br />

Set RDY Clear RDY Setting of RDY Bit<br />

0 1 RDY bit is cleared to 0.<br />

1 0 RDY bit is set to 1.<br />

Other than above RDY bit is not changed.<br />

Caution Set IE bit and RDY bit always separately.<br />

Remark m = 0 to 15<br />

R01UH0317EJ0004 Rev. 0.04 879<br />

Feb. 22, 2013

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