RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 15 STEPPER MOTOR CONTROLLER/DRIVER (5) Compare control registers (MCMPCk) (k = 1 to 4) The 8-bit MCMPCk registers control the operation of the corresponding compare registers and the output direction of the PWM pin. These registers can be read/written in 8-bit or 1-bit units. This register is cleared by any reset. Figure 15-3. Format of Compare Control Registers (MCMPCk) (1/2) Address: F016AH, F016CH, F016EH, F0158H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 MCMPCk AOUTk TWINk ZPDk Note TENk ADBk1 ADBk0 DIRk1 DIRk0 Note This bit may be written, but writing is ignored. AOUTk Output pins for sine and cosine signals 0 The PWM signals for sine and cosine side are output to those pins that are selected by bits DIRk0 and DIRk1. At all other pins, the output signal is 0 (SMVSS level). 1 The PWM signal for the sine side is output to pins SMk1 and SMk2. The PWM signal for the cosine side is output to pins SMk3 and SMk4. TWINk 0-point detection timing window 0 Disable writing to ZPD bit from the comparator (No 0-point detection) 1 Enable writing to ZPD bit from the comparator (0-point detection) ZPDk Induced voltage detection bit for 0-point detection (Read only) 0 No induced voltage detection (0-point detection) 1 Induced voltage detection (No 0-point detection) TENk Transfer enable control bit 0 MCMPk0/MCMPk1 master-to-slave register copy is disabled. New data can be written to compare registers MCMPk0 or MCMPk1. 1 MCMPk0/MCMPk1 master-to-slave register copy is enabled. The copy process will take place when CNT0 overflows. Don't write to compare registers MCMPk0 or MCMPk1 while MCMPCk.TEN = 1. Remark This bit functions as a control bit and status flag. It is automatically reset to zero upon the next timer counter overflow. ADBk1 1-bit addition circuit control (cosine side) 0 No 1-bit addition to PWM signal 1 1-bit addition to PWM signal ADBk0 1-bit addition circuit control (sine side) 0 No 1-bit addition to PWM signal 1 1-bit addition to PWM signal R01UH0317EJ0004 Rev. 0.04 953 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 15 STEPPER MOTOR CONTROLLER/DRIVER Figure 15-3. Format of Compare Control Registers (MCMPCk) (2/2) DIRk1 DIRk0 Selected output pins 0 0 Quadrant 1: SMk1 (sin +), SMk3 (cos +) 0 1 Quadrant 2: SMk1 (sin +), SMk4 (cos –) 1 0 Quadrant 3: SMk2 (sin –), SMk4 (cos –) 1 1 Quadrant 4: SMk2 (sin –), SMk3 (cos +) Selects the output pins for the PWM signals. Bits DIR1 and DIR0 address the quadrant to be activated by sine and cosine. The PWM signal is routed to the specific pin with respect to the sin/cos of each quadrant. At the other output pins, the output level is SMVSS. Remark These bits are only considered if bit AOUT is set to 0. R01UH0317EJ0004 Rev. 0.04 954 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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