RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 12 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission/reception mode) Figure 12-48. Timing Chart of Master Transmission/Reception (in Continuous Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn SDRmn SCKp pin SIp pin Shift register mn SOp pin INTCSIp MDmn0 TSFmn BFFmn Transmit data 1 Transmit data 2 Receive data 1 Transmit data 3 Receive data 3 Receive data 2 Write Write Write Read Read Read Receive data 1 Receive data 2 Receive data 3 Reception & shift operation Reception & shift operation Reception & shift operation Transmit data 1 Transmit data 2 Transmit data 3 Data transmission/reception (8-bit length) Data transmission/reception (8-bit length) Data transmission/reception (8-bit length) (Note 1) (Note 2) (Note 2) Notes 1. When transmit data is written to the SDRmn register while BFFmn = 1, the transmit data is overwritten. 2. The transmit data can be read by reading the SDRmn register during this period. At this time, the transfer operation is not affected. Caution The MDmn0 bit can be rewritten even during operation. However, rewrite it before transfer of the last bit is started, so that it has been rewritten before the transfer end interrupt of the last transmit data. Remarks 1. to in the figure correspond to to in Figure 12-49 Flowchart of Master Transmission/Reception (in Continuous Transmission/Reception Mode). 2. m: Unit number (m = 0, 1), n: Channel number (n = 0, 1), p: CSI number (p = 00, 01, 10) R01UH0317EJ0004 Rev. 0.04 617 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-49. Flowchart of Master Transmission/Reception (in Continuous Transmission/Reception Mode) Writing 1 to MDmn0 bit Starting CSI communication Setting SAU1EN and SAU0EN bits of PER0 register to 1 Setting operation clock by SPSm register SMRmn, SCRmn: Setting communication SDRmn[15:9]: Setting transfer rate SOm, SOEm: Setting output and SCKp output No Yes Port manipulation Writing 1 to SSmn bit Writing transmit data to SDRmn register Buffer empty interrupt generated? Yes Reading receive data from SDRmn register Communication data exists? No Clearing 0 to MDmn0 bit TSFmn = 1? Yes Transfer end interrupt generated? Yes Reading receive data from SDRmn register Communication continued? No Writing 1 to STmn bit Clearing SAU1EN and SAU0EN bits of PER0 register to 0 End of communication Perform initial setting when SEmn = 0. Select the buffer empty interrupt. Caution After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more clocks have elapsed. Remark to in the figure correspond to to in Figure 12-48 Timing Chart of Master Transmission/Reception (in Continuous Transmission/Reception Mode). R01UH0317EJ0004 Rev. 0.04 618 Feb. 22, 2013 No No Yes
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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12.5.3 Master transmission/receptio
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14.9.1 Message reception ..........
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19.2 Configuration of DMA Controlle
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28.1.1 Programming Environment.....
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34.2 64-pin products 1276 R5F10CLDx
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RL78/D1A User’s Manual: Hardware
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