RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 4 PORT FUNCTIONS Figure 4-54. Format of Port input mode Register (4/4) (100-pin products) Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PIM0 0 0 0 0 0 0 PIM01 0 F0040 00H R/W PIM1 PIM17 0 0 0 0 0 PIM11 PIM10 F0041 00H R/W PIM3 0 0 0 0 0 0 PIM31 0 F0043 00H R/W PIM5 PIM57 PIM56 PIM55 0 0 PIM52 PIM51 PIM50 F0045 00H R/W PIM6 0 0 0 0 PIM63 0 PIM61 0 F0046 00H R/W PIM7 0 0 0 0 0 0 0 PIM70 F0047 00H R/W PIM13 0 0 PIM135 0 0 0 0 0 F004D 00H R/W PIMmn PIMmn pin input threshold selection 0 Schmit1 input mode 1 Schmit3 input mode (m = 0, 1, 3, 5 to 7, and 13 ; n = 0 to 7) Bit name PIM01 PIM17 PIM11 PIM10 PIM31 PIM57 PIM56 PIM55 Port input function P01 /CRxD0 P17 P11 /LRxD1 /SI00 P10 /SCK00 P31 /SDA11 R01UH0317EJ0004 Rev. 0.04 227 Feb. 22, 2013 P57 P56 /SCK01 Bit name PIM52 PIM51 PIM50 PIM63 PIM61 PIM70 PIM135 - Port input function P52 /SI10 P51 /SCK10 P50 /SDA11 P63 /CRxD1 P61 /SDA11 P70 /CRxD0 /LRxD0 P135 /CRxD1 P55 /SI01 -
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 4 PORT FUNCTIONS (5) Port output mode register (POM) This register sets the output mode of P30, P31, P50, P60, P61, P136 in 1-bit units. N-ch open drain output (VDD tolerance) mode can be selected during serial communication with an external device of the different potential, and for the SDA11 and SCL11 pins during simplified I2C communication with an external device of the same potential. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. (a) 48-pin products (b) 64-pin products (c) 80-pin products (d) 100-pin products Figure 4-55. Format of Port input mode Register Symbol 7 6 5 4 3 2 1 0 Address After reset R/W POM 0 0 0 0 POM3 POM2 POM1 POM0 F006F 00H R/W Symbol 7 6 5 4 3 2 1 0 Address After reset R/W POM 0 0 0 0 POM3 POM2 POM1 POM0 F006F 00H R/W Symbol 7 6 5 4 3 2 1 0 Address After reset R/W POM 0 0 0 0 POM3 POM2 POM1 POM0 F006F 00H R/W Symbol 7 6 5 4 3 2 1 0 Address After reset R/W POM 0 0 POM5 POM4 POM3 POM2 POM1 POM0 F006F 00H R/W POMn Port output mode selection (n = 0 to 5) 0 Normal output (CMOS) mode 1 Nch-OD output (VDD tolerance) mode Bit name POM5 POM4 POM3 POM2 POM1 POM0 Port output function P50 /TO02 /SDA11 P136 /TO00 /SCL11 P31 /TO21 /SDA11 P30 /TO20 /SCL11 P61 /TO21 /SDA11 P60 /TO20 /SCL11 Remark If use the alternate function of IIC, port output need to be set as Nch open-drain (Nch-OD) output. At that time, POM forces on-chip pull-up resistors should not be active (disabled by circuit). R01UH0317EJ0004 Rev. 0.04 228 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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34.2 64-pin products 1276 R5F10CLDx
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