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RL78/D1A User's Manual: Hardware - Renesas

RL78/D1A User's Manual: Hardware - Renesas

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Under development<br />

Preliminary document<br />

Specifications in this document are tentative and subject to change.<br />

<strong>RL78</strong>/<strong>D1A</strong> CHAPTER 27 OPTION BYTE<br />

27.4 Setting of Option Byte<br />

The user option byte and on-chip debug option byte can be set using the assembler linker option, in addition to<br />

describing to the source. When doing so, the contents set by using the linker option take precedence, even if descriptions<br />

exist in the source, as mentioned below.<br />

A software description example of the option byte setting is shown below.<br />

OPT CSEG OPT_BYTE<br />

DB 36H ; Does not use interval interrupt of watchdog timer,<br />

; Enables watchdog timer operation,<br />

; Window open period of watchdog timer is 50%,<br />

; Overflow time of watchdog timer is 2 9 /fIL,<br />

; Stops watchdog timer operation during HALT/STOP mode<br />

DB 7AH ; Select 2.75 V for VLVDL<br />

; Select rising edge 2.92 V, falling edge 2.86 V for VLVDH<br />

; Select the interrupt & reset mode as the LVD operation mode<br />

stops clock monitoring<br />

DB 0C9H ; Select the HS (high speed main) mode as the flash operation mode<br />

and 16 MHz as the frequency of the high-speed on-chip oscillator<br />

DB 85H ; Enables on-chip debug operation, does not erase flash memory<br />

data when security ID authorization fails<br />

When the boot swap function is used during self programming, 000C0H to 000C3H is switched to 020C0H to 020C3H.<br />

Describe to 020C0H to 020C3H, therefore, the same values as 000C0H to 000C3H as follows.<br />

OPT2 CSEG AT 020C0H<br />

DB 36H ; Does not use interval interrupt of watchdog timer,<br />

; Enables watchdog timer operation,<br />

; Window open period of watchdog timer is 50%,<br />

; Overflow time of watchdog timer is 2 9 /fIL,<br />

; Stops watchdog timer operation during HALT/STOP mode<br />

DB 7AH ; Select 2.75 V for VLVDL<br />

; Select rising edge 2.92 V, falling edge 2.86 V for VLVDH<br />

; Select the interrupt & reset mode as the LVD operation mode<br />

stops clock monitoring<br />

DB 0C9H ; Select the HS (high speed main) mode as the flash operation mode<br />

and 16 MHz as the frequency of the high-speed on-chip oscillator<br />

DB 85H ; Enables on-chip debug operation, does not erase flash memory<br />

data when security ID authorization fails<br />

Caution To specify the option byte by using assembly language, use OPT_BYTE as the relocation attribute<br />

name of the CSEG pseudo instruction. To specify the option byte to 020C0H to 020C3H in order to<br />

use the boot swap function, use the relocation attribute AT to specify an absolute address.<br />

R01UH0317EJ0004 Rev. 0.04 1159<br />

Feb. 22, 2013

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