RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 6 TIMER ARRAY UNIT 6.4 Channel Output (TOmn Pin) Control 6.4.1 TOmn pin output circuit configuration Interrupt signal of the master channel (INTTMmn) Interrupt signal of the slave channel (INTTMmp) Controller The following describes the TOmn pin output circuit. Figure 6-40. Output Circuit Configuration TOLmn TOMmn TOEmn R01UH0317EJ0004 Rev. 0.04 391 Feb. 22, 2013 TOmn register Set Reset/toggle TOmn write signal Internal bus TOmn pin When TOMmn = 0 (toggle mode), the set value of the TOLmn register is ignored and only INTTMmp (slave channel timer interrupt) is transmitted to the TOmn register. When TOMmn = 1 (combination operation mode), both INTTMmn (master channel timer interrupt) and INTTMmp (slave channel timer interrupt) are transmitted to the TOmn register. At this time, the TOLmn register becomes valid and the signals are controlled as follows: When TOLmn = 0: Forward operation (INTTMmn set, INTTMmp reset) When TOLmn = 1: Reverse operation (INTTMmn reset, INTTMmp set) When INTTMmn and INTTMmp are simultaneously generated, (0% output of PWM), INTTMmp (reset signal) takes priority, and INTTMmn (set signal) is masked. Remark m: Unit number (m = 0 to 2), n: Channel number, p: Slave channel number When TOEmn = 1, INTTMmn (master channel timer interrupt) and INTTMmp (slave channel timer interrupt) are transmitted to the TOmn register. Writing to the TOmn register (TOmn write signal) becomes invalid. When TOEmn = 1, the TOmn pin output never changes with signals other than interrupt signals. To initialize the TOmn pin output level, it is necessary to set TOEmn = 0 and to write a value to TOmn. When TOEmn = 0, writing to TOmn bit to the target channel (TOmn write signal) becomes valid. When TOEmn = 0 neither INTTMmn (master channel timer interrupt) nor INTTMmp (slave channel timer interrupt) is transmitted to TOmn register. The TOmn register can always be read, and the TOmn pin output level can be checked. Remark m: Unit number (m = 0 to 2), n: Channel number, p: Slave channel number
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 6 TIMER ARRAY UNIT 6.4.2 TOmn pin output setting The following figure shows the procedure and status transition of TOmn output pin from initial setting to timer operation start. Figure 6-41. Status Transition from Timer Output Setting to Operation Start TCRmn (Counter) Timer alternate-function pin Timer output signal TOmn TOEmn Undefined value (FFFFH after reset) Write operation enabled period to TOmn Set the TOMmn Set the TOLmn The operation mode of timer output is set. Hi-Z Write operation disabled period to TOmn Set the TOmn Set the TOEmn Set the port to Timer operation start output mode TOMmn bit (0: Toggle mode, 1: Combination operation mode) TOLmn bit (0: Forward output, 1: Reverse output) The timer output signal is set to the initial status by setting TOmn. The timer output operation is enabled by writing 1 to TOEmn (writing to TOmn is disabled). The port I/O setting is set to output (see 6.3 (19) Port mode registers 0 to 9, 13 to 15). The timer operation is enabled (TSmn = 1). Remark m: Unit number (m = 0 to 2) n: Channel number (n = 0 to 7) R01UH0317EJ0004 Rev. 0.04 392 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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