RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF) A BF transmission operation is started when a BF transmission trigger (UFnBTT) is set. A low level of bits 13 to 20 specified by the BF length selection bits (UFnBLS2 to UFnBLS0) is output to the LTxDn pin. A transmission interrupt request signal (INTLTn) is generated when the BF transmission is started. After the BF transmission ends, the BF transmission state is automatically released and operation is returned to normal UART transmission mode. The transmission operation stays in a wait state until the data to be transmitted is written to the UFnTX register, or a BF transmission trigger (UFnBTT) is set. Start the next transmission operation after having confirmed that the BF has been received normally according to the reception complete interrupt (INTLRn) during the BF transmission or the status interrupt (INTLSn). fCLK LTxDn pin Prescaler clock Transmission baud rate clock INTLTn (UFnITS = 0) UFnTSF flag Figure 13-33. BF Transmission Timing Example First bit Second bit STOP1 Transmission processing start Transmission processing end Transmission baud rate period Transmission baud rate period Transmission baud rate period Set by writing UFnTX register Cleared when next transmit data does not exist Caution When the stop bit length is set to 2 bits (UFnSL = 1), the transmission status flag (UFnTSF) is cleared when the second stop bit has been completed. Remark n = 0, 1 R01UH0317EJ0004 Rev. 0.04 731 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF) 13.5.6 BF reception Figure 13-34 describes the processing of BF reception in LIN communication. Figure 13-34. BF Reception Processing Flow START Baud rate setting (UFnCTL1 register) Receive data level setting (UFnOPT0 register) Various mode settings (UFnOPT1) Noise filter, INTLTn timing settings (UFnOPT2) Various mode settings, enabling reception (UFnCTL0) INTLSn signal generated? Caution Set the following values when performing BF transmission. The input logic level is normal input (UFnRDL = 0). Communication direction control is LSB first (UFnDIR = 1). The parity selection bit is no parity bit output (UFnPS1, UFnPS0 = 00B). The data character length is 8 bits (UFnCL = 1). Transmission interrupt is when starting transmission (UFnITS = 0). BF reception enable mode during communication (UFnMD1, UFnMD0 = 10B) as the mode. END Yes Remarks 1. Figure 13-34 shows the reception processing flow of LIN communication in BF reception enable mode during communication (UFnMD1, UFnMD0 = 10B). See 13.7 LIN Communication Automatic Baud Rate Mode for when in automatic baud rate mode (UFnMD1, UFnMD0 = 11B). 2. See (2) of 13.11 Cautions on Use for details of starting LIN-UART. 3. n = 0, 1 R01UH0317EJ0004 Rev. 0.04 732 Feb. 22, 2013 No
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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RL78/D1A User’s Manual: Hardware
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