RL78/D1A User's Manual: Hardware - Renesas

Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 5 CLOCK GENERATOR
Figure 5-8. Format of Peripheral Enable Registers 0, 1 (PER0, PER1) (2/3)
Address: F00F0H After reset: 00H R/W
Symbol
PER0 RTCEN LIN1EN LIN0EN SAU1EN SAU0EN TAU2EN TAU1EN TAU0EN
Address: F00F1H After reset: 00H R/W: Bits 0 to 3 and 6 (Read Only)
Symbol
PER1 ADCEN 0 MTRCEN SGEN 0 0 0 0
LIN0EN Control of LIN-UART0 converter input clock supply
0 Stops input clock supply.
SFR used by LIN-UART0 cannot be written.
LIN-UART0 is in the reset status.
1 Supplies input clock.
SFR used by LIN-UART0 can be read and written.
SAU1EN Control of serial array unit 1 input clock supply
0 Stops input clock supply.
SFR used by the serial array unit 1 cannot be written.
The serial array unit 1 is in the reset status.
1 Enables input clock supply.
SFR used by the serial array unit 1 can be read and written.
SAU0EN Control of serial array unit 0 input clock supply
0 Stops input clock supply.
SFR used by the serial array unit 0 cannot be written.
The serial array unit 0 is in the reset status.
1 Enables input clock supply.
SFR used by the serial array unit 0 can be read and written.
TAU2EN Control of serial array unit 2 input clock supply
0 Stops input clock supply.
SFR used by timer array unit 2 cannot be written.
Timer array unit 2 is in the reset status.
1 Enables input clock supply.
SFR used by timer array unit 2 can be read and written.
R01UH0317EJ0004 Rev. 0.04 282
Feb. 22, 2013