RL78/D1A User's Manual: Hardware - Renesas

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Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 24 VOLTAGE DETECTOR
24.1 Functions of Voltage Detector
The voltage detector (LVD) has the following functions.
CHAPTER 24 VOLTAGE DETECTOR
The LVD circuit compares the supply voltage (VDD) with the detection voltage (VLVDH, VLVDL), and generates an
internal reset or internal interrupt signal.
The detection level for the power supply detection voltage (VLVDH, VLVDL) can be selected by using the option byte as
one of 6 levels (For details, see CHAPTER 27 OPTION BYTE).
Operable in STOP mode.
The following three operation modes can be selected by using the option byte.
(a) Interrupt & reset mode (option byte LVIMDS1, LVIMDS0 = 1, 0)
For the two detection voltages selected by the option byte 000C1H/020C1H, the high-voltage detection level
(VLVDH) is used for generating interrupts and ending resets, and the low-voltage detection level (VLVDL) is used for
triggering resets.
(b) Reset mode (option byte LVIMDS1, LVIMDS0 = 1, 1)
The detection voltage (VLVD) selected by the option byte 000C1H/020C1H is used for triggering and ending resets.
(c) Interrupt mode (option byte LVIMDS1, LVIMDS0 = 0, 1)
The detection voltage (VLVD) selected by the option byte 000C1H/020C1H is used for generating interrupts/reset
release.
Two detection voltages (VLVDH, VLVDL) can be specified in the interrupt & reset mode, and one (VLVD) can be specified in
the reset mode and interrupt mode.
The reset and interrupt signals are generated as follows according to the option byte (LVIMDS0, LVIMDS1) selection.
Interrupt & reset mode
(LVIMDS1, LVIMDS0 = 1, 0)
Generates an internal interrupt signal
when VDD < VLVDH, and an internal reset
when VDD < VLVDL.
Releases the reset signal when VDD
VLVDH.
Reset mode
(LVIMDS1, LVIMDS0 = 1, 1)
Generates an internal reset signal when
VDD < VLVD and releases the reset signal
when VDD VLVD.
Interrupt mode
(LVIMDS1, LVIMDS0 = 0, 1)
Generates an internal interrupt signal
when VDD drops lower than VLVD (VDD <
VLVD) or when VDD becomes VLVD or
higher
(VDD VLVD).
Releases the reset signal when VDD
VLVD at power on.
While the voltage detector is operating, whether the supply voltage or the input voltage from an external input pin is
more than or less than the detection level can be checked by reading the voltage detection flag (LVIF: bit 0 of the voltage
detection register (LVIM)).
Bit 0 (LVIRF) of the reset control flag register (RESF) is set to 1 if reset occurs. For details of the RESF register, see
CHAPTER 22 RESET FUNCTION.
R01UH0317EJ0004 Rev. 0.04 1114
Feb. 22, 2013