RL78/D1A User's Manual: Hardware - Renesas

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R01UH0317EJ0004 Rev. 0.04 1323 Feb. 22, 2013 Necessary WAIT I/O register(SFR) name R/W Bit R/W Address READ(MIN.) READ(MAX.) WRITE(MIN.) WRITE(MAX.) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1 8 16 7 6 5 4 3 2 1 0 - - - - FFFD0 - - - - FFFD1 - - - - FFFD2 - - - - FFFD3 - - - - FFFD4 - - - - FFFD5 - - - - FFFD6 - - - - FFFD7 - - - - FFFD8 - - - - FFFD9 - - - - FFFDA IF2 (Interrupt request flag register 2) - - E - - - - - - - - IF2L (Interrupt request flag register 2L) E E - E E E E E E E E C0RECIF C0WUPIF C0ERRIF C1WUPIF C1ERRIF TMIF07 TMIF06 TMIF05 E E E E E E E E IF2H (Interrupt request flag register 2H) E E - E E E E E E E E FLIF C1RECIF MDIF TMIF13 TMIF12 TMIF11 TMIF10 C0TRXIF E E E E E E E E IF3 (Interrupt request flag register 3) - - E - - - - - - - - IF3L (Interrupt request flag register 3L) E E - E E E E E E E E TMIF22 TMIF21 TMIF20 TMIF17 TMIF16 TMIF15 TMIF14 C1TRXIF E E E E E E E E IF3H (Interrupt request flag register 3H) E E - R R R E E E E E DMAIF3 DMAIF2 TMIF26 TMIF24 TMIF23 - - - E E E E E MK2 (Interrupt mask flag register 2) - - E - - - - - - - - MK2L (Interrupt mask flag register 2L) E E - E E E E E E E E C0RECMK C0WUPMK C0ERRMK C1WUPMK C1ERRMK TMMK07 TMMK06 TMMK05 E E E E E E E E MK2H (Interrupt mask flag register 2H) E E - E E E E E E E E FLMK C1RECMK MDMK TMMK13 TMMK12 TMMK11 TMMK10 C0TRXMK E E E E E E E E MK3 (Interrupt mask flag register 3) - - E - - - - - - - - MK3L (Interrupt mask flag register 3L) E E - E E E E E E E E TMMK22 TMMK21 TMMK20 TMMK17 TMMK16 TMMK15 TMMK14 C1TRXMK E E E E E E E E MK3H (Interrupt mask flag register 3H) E E - R R R E E E E E DMAMK3 DMAMK2 TMMK26 TMMK24 TMMK23 - - - E E E E E PR02 (Priority specification flag register 02) - - E - - - - - - - - PR02L (Priority specification flag register 02L) E E - E E E E E E E E C0RECPR0 C0WUPPR0 C0ERRPR0 C1WUPPR0 C1ERRPR0 TMPR007 TMPR006 TMPR005 E E E E E E E E PR02H (Priority specification flag register 02H) E E - E E E E E E E E FLPR0 C1RECPR0 MDPR0 TMPR013 TMPR012 TMPR011 TMPR010 C0TRXPR0 E E E E E E E E PR03 (Priority specification flag register 03) - - E - - - - - - - - PR03L (Priority specification flag register 03L) E E - E E E E E E E E TMPR022 TMPR021 TMPR020 TMPR017 TMPR016 TMPR015 TMPR014 C1TRXPR0 E E E E E E E E 1323 RL78/D1A APPENDIX A NUMBER OF WAIT CYCLES TO ACCESS I/O REGISTERS Specifications in this document are tentative and subject to change. Under development Preliminary document
R01UH0317EJ0004 Rev. 0.04 1324 Feb. 22, 2013 Necessary WAIT I/O register(SFR) name R/W Bit R/W Address READ(MIN.) READ(MAX.) WRITE(MIN.) WRITE(MAX.) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1 8 16 7 6 5 4 3 2 1 0 - - - - FFFDB - - - - FFFDC - - - - FFFDD - - - - FFFDE - - - - FFFDF - - - - FFFE0 - - - - FFFE1 - - - - FFFE2 - - - - FFFE3 - - - - FFFE4 - - - - FFFE5 PR03H (Priority specification flag register 03H) E E - R R R E E E E E DMAPR03 DMAPR02 TMPR026 TMPR024 TMPR023 - - - E E E E E PR12 (Priority specification flag register 12) - - E - - - - - - - - PR12L (Priority specification flag register 12L) E E - E E E E E E E E C0RECPR1 C0WUPPR1 C0ERRPR1 C1WUPPR1 C1ERRPR1 TMPR107 TMPR106 TMPR105 E E E E E E E E PR12H (Priority specification flag register 12H) E E - E E E E E E E E FLPR1 C1RECPR1 MDPR1 TMPR113 TMPR112 TMPR111 TMPR110 C0TRXPR1 E E E E E E E E PR13 (Priority specification flag register 13) - - E - - - - - - - - PR13L (Priority specification flag register 13L) E E - E E E E E E E E TMPR122 TMPR121 TMPR120 TMPR117 TMPR116 TMPR115 TMPR114 C1TRXPR1 E E E E E E E E PR13H (Priority specification flag register 13H) E E - R R R E E E E E DMAPR13 DMAPR12 TMPR126 TMPR124 TMPR123 - - - E E E E E IF0 (Interrupt request flag register 0) - - E - - - - - - - - IF0L (Interrupt request flag register 0L) E E - E E E E E E E E PIF5 PIF4 PIF3 PIF2 PIF1 PIF0 LVIIF WDTIIF E E E E E E E E IF0H (Interrupt request flag register 0H) E E - E E E E E E E E LTIF0 ITIF RTCIF DMAIF1 DMAIF0 CSIIF01 CSIIF00 CLMIF E E E E E E E E IF1 (Interrupt request flag register 1) - - E - - - - - - - - IF1L (Interrupt request flag register 1L) E E - E E E E E E E E TMIF03 TMIF02 TMIF01 TMIF00 SGIF PIFLR0 LSIF0 LRIF0 E E E E E E E E IF1H (Interrupt request flag register 1H) E E - E E E E E E E E TMIF04 IICIF11 CSIIF10 PIFLR1 LSIF1 LRIF1 LTIF1 ADIF E E E E E E E E MK0 (Interrupt mask flag register 0) - - E - - - - - - - - MK0L (Interrupt mask flag register 0L) E E - E E E E E E E E PMK5 PMK4 PMK3 PMK2 PMK1 PMK0 LVIMK WDTIMK E E E E E E E E MK0H (Interrupt mask flag register 0H) E E - E E E E E E E E LTMK0 ITMK RTCMK DMAMK1 DMAMK0 CSIMK01 CSIMK00 CLMMK E E E E E E E E 1324 RL78/D1A APPENDIX A NUMBER OF WAIT CYCLES TO ACCESS I/O REGISTERS Specifications in this document are tentative and subject to change. Under development Preliminary document
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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12.5.3 Master transmission/receptio
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14.9.1 Message reception ..........
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19.2 Configuration of DMA Controlle
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